Saturation Limit for Speed and Current Control in IPMSM

Hi,

I am working on FOC of IPMSM. I am using three PI controllers. One for speed control and two for current control (id and iq).

My question is:

1. How to design practical saturation limit of PI control for speed control and
2. How to design practical saturation limit of PI control for id and iq control

Answer 1

[Dakai Hu]

Hello Sanjeev,

Here is something to consider for the questions you asked:

1. How to design practical saturation limit of PI control for speed control

The output of your speed loop's PI controller is a current command for Iq, or for both Id and Iq. Particularly for IPMSM, Id current command should always be negative (or 0). If you know the current constraint Ismax for your current loop, then a practical saturation limit for the speed loop's PI should be Iq: [-Ismax, Ismax]. Id: [-Ismax, 0].

1. How to design practical saturation limit of PI control for id and iq control

The output of your current loop's PI is voltage reference Vd and Vq. If you are not using a per-unitized system, then the constraint for Vd and Vq depends on the PWM strategy you are adopting. For SVPWM, the linear maximum modulation voltage is calculated by Vdc/sqrt(3). Therefore the saturation limit for both current loop PI controllers should be [-Vdc/sqrt(3), Vdc/sqrt(3)].