How to optimize multiplications with hdl coder

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Dominik Hiltbrunner
Dominik Hiltbrunner on 21 Jul 2020
Edited: Kiran Kintali on 24 Jul 2020
Hello community
I'm using Simulink to generate VHDL code. The system runs on 2.5 MHz sample rate and is supposed to run on a target architecture with 100 MHz.
The model uses quite a lot of constant multiplications, too many to fit on a FPGA, i.e. the available DSP blocks are not sufficient.
Since the FPGA runs on a much faster clock than the Simulink model, I want to use the 40 clock cycles to optimize the system by implementing the multiplications based on the shift and add algorithm or by multiplexing between the hardware multipliers.
1) Is it possible to automatically implement the shift and add approach with the hdl coder? If yes, how?
2) Is it possible to automatically implement the multiplexing approach with the hdl coder? If yes, how?
3) Is it possible to automatically approximate a constant with the nearest fixpoint representation and then implement the multiplication as a shift operation only? If yes, how?
  1 Comment
Kiran Kintali
Kiran Kintali on 21 Jul 2020
Can you share your design? What are the sizes of multipliers you have in mind?
ConstMultiplierOptimization (CSD/FCSD) would be a good choice if you have Gain blocks (multiplication by constants) and you do not want to use hard multipliers on the FPGA.

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Answers (1)

Kiran Kintali
Kiran Kintali on 21 Jul 2020
ConstMultiplierOptimization
The ConstMultiplierOptimization implementation parameter lets you specify use of canonical signed digit (CSD) or factored CSD optimizations for processing coefficient multiplier operations in the generated code.
The following table shows the ConstMultiplierOptimization parameter values.
ConstMultiplierOptimization SettingDescription
'none'
(Default)By default, HDL Coder does not perform CSD or FCSD optimizations. Code generated for the Gain block retains multiplier operations.
'CSD'When you specify this option, the generated code decreases the area used by the model while maintaining or increasing clock speed, using canonical signed digit (CSD) techniques. CSD replaces multiplier operations with add and subtract operations. CSD minimizes the number of addition operations required for constant multiplication by representing binary numbers with a minimum count of nonzero digits.
'FCSD'This option uses factored CSD (FCSD) techniques, which replace multiplier operations with shift and add/subtract operations on certain factors of the operands. These factors are generally prime but can also be a number close to a power of 2, which favors area reduction. This option lets you achieve a greater area reduction than CSD, at the cost of decreasing clock speed.
'auto'
When you specify this option, HDL Coder chooses between the CSD or FCSD optimizations. The coder chooses the optimization that yields the most area-efficient implementation, based on the number of adders required. When you specify 'auto', the coder does not use multipliers, unless conditions are such that CSD or FCSD optimizations are not possible (for example, if the design uses floating-point arithmetic).
The ConstMultiplierOptimization parameter is available for the following blocks:
  • Gain
  • Stateflow® chart
  • Truth Table
  • MATLAB Function
  • MATLAB System
  9 Comments
Dominik Hiltbrunner
Dominik Hiltbrunner on 24 Jul 2020
I found the problem: it is the word length. If I reduce the word size to 64 bit, then Simulink implements CDS and FCDS. If I reduce it further to 32 bit, then it also implements the multiplier slicing.

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