Mostly the formal verification methodology tends to give counter example whenever the eqivalence is not matched.
But if it giving out falsified option and not able to generate the counter-example corresponding to it then the design must have been very unique or tool might not be able to produce the example. This will require looking into the model first.
On contrary , you can Try clicking on "Create harness model" in the Results window and running the simulation.
The objectives will no longer be falsified only when the design error in the model is fixed.
Hope it helps !