Error with cosimulation on tunable parameters
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Hello all!
I'm having trouble with conducting FPGA In the Loop. I'm getting this error regarding cosimulation and tunable parameters. Do you know of a solution or a bypass? The objective is to do a FPGA in the loop simulation of a field oriented control based current controller.
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/438178/image.png)
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Réponses (2)
Kiran Kintali
le 2 Déc 2020
This is a limitation in the cosimulation test bench generation.
Can you consider using stand-alone testbench with HDL Simulator?
Kiran Kintali
le 8 Déc 2020
yes, You can target zed board using HDL Coder. FPGA data capture is another good way to capture signals. please contact support@mathworks.com
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