I'm trying to implement a limited counter which has a variable upper limit, i.e. the upper limit is given by a signal.
This proposed solution does this. The problem is that this solution is not HDL code generation compatible. If I try to generate VHDL code, I get the follwing error from the resettable delay block:
Only 'Level' external reset mode on the Delay block is supported in 'Classic' mode.
If I set the External reset to "Level" mode, the behaviour is no longer correct.
What do I have to do in order to create a resettable delay block that behaves in the same way as a flip flop that resets on the rising edge?
Furthermore, what is the "Classic mode" in this error message? I cannot find an answer to this in the documentation.