FPGA in the Loop minimum clock frequency

I want to do an FPGA simulation with a small clock frequency. However filWizard does not allow to give smaller than 5MHz to the design. How to achieve this? Thanks.

Answer 1

[Madhu Varshini]

To get FPGA simulation with a small clock frequency, try increasing oversampling factor of the design. The Oversampling factor delays output, thereby clock frequency can go low.

You can refer the following link for more detail about target frequency:

https://www.mathworks.com/help/hdlverifier/ug/block-generation-with-the-fil-wizard.html

You can refer the following link to get more information about FPGA system clock frequency, you can refer the following link:

https://www.mathworks.com/help/hdlverifier/ug/system-object-generation-with-the-fil-wizard.html

You can refer the following link to get more detail about relation between sampling frequency, FPGA clock frequency and oversampling factor, you can refer the following link.

https://in.mathworks.com/help/physmod/sps/ug/sample-time-relationship-between-hdl-implementation-model-and-simscape-algorithm.html