HDL Code Generation Block Support
2 vues (au cours des 30 derniers jours)
I understand that Simulink offers specific HDL-support blocks and a HDL environment for models intended for HDL code generation. These are advised by Mathworks. However is it possible to use other "normal blocks" for HDL code generation and can it only be designed and generated in the HDL environment?
Much like C code generation, can you simply design your model, make sure its compatible, press a button and boom you have code.
Any information would be appreciated.
Kiran Kintali le 16 Fév 2021
HDL Coder specific library in Simulink provides few HDL friendly blocks like RAM, FIFO etc., that are suited for HDL code generation but rest of the ~250blocks supported in Simulink including blocks like MATLAB function block, Stateflow, various subsystem semantic blocks (enabled, triggered, synchronous subsystems) allow you build any custom Math algorithm (with fixed-step discrete solver) and generate Synthesizable VHDL/Verilog code.
See list of HDL Coder User Stories showcasing customers building ASIC/FPGA applications using HDL Coder generated code.