Error beetween two methods: Simulink and Verilog(after convert by HDL coder)

Dear My friends!

Now i have some problems in HDL simulink coder that need your helping. When i convert my code from simulink to verilog and after that i cosimulate it with modelsim, I have got an error between two results.

http://i1297.photobucket.com/albums/ag25/Dung_Pham_Van/error_zps3efd15af.gif

Anyone have any experimental to solve this problem?? please give me some suggestions.

Thanks with best regard!

[Pham Van Dung]

Sorry, i don't know how to add my pictures in my question..Hope i can get many answers .Thankyou so much!

Answer 1

[Tim McBrayer]

It looks like the two waveforms are identical, but time-shifted. Often Simulink HDL Coder will need to insert latency into the HDL design based on the configuration and optimizations chosen. The amount of introduced latency is reported on the MATLAB console and also in the HTML report, if generated. Could this be the source of the shift? Are the results identical save for the time shift?

[Pham Van Dung]

Dear Tim McBrayer

Thanks for your suggestions! i already find where can i insert latency in the HDL design, but I can't. Because i used to use HDL Workflow Advisor Tasks, and it design HDL block automatically. I also have many simulink files that have this problem! How can I solve this problem?Can I send to you my files?

Best regards!

Pham Van Dung