The short answer: neither block you mention can have HDL code generated for it by HDL Coder.
A model destined for HDL code generation is divided into two parts: the subsystem you wish to convert to HDL, and the model surrounding the target subsystem (the testbench). The testbench can contain any blocks, and any sources. This corresponds to the inputs to your FPGA.
The target subsystem can only contain blocks supported for HDL code generation. To see a library containing the complete set of supported blocks, type 'hdllib' at the MATLAB prompt. This shows that neither the step input nor the clock block are supported for HDL code generation.
The most straightforward use of these blocks would be to place them outside your target subsystem, providing this stimulus as an input to your design and ultimately to your FPGA (or other physical implementation). The difficulty in implementing these blocks in HDL is that they both refer to an absolute time. Short of having an actual clock on the target hardware (which FPGAs typically do not have) there's no convenient way to realize these blocks in hardware.
Determining the time passed since some particular event is pretty straightforward, using a resettable counter and knowing the frequency that you run the clock at. For example, with a 10MHz clock, if you count to 10^7, you've waited one second. A hardware-friendly counter is available in the HDL Counter block, available in the HDL Demo library. This library can be found in the hdllib previously opened, or directly by running 'hdldemolib' in MATLAB.