FPGA Implementation of the Gray Scale Image Erosion Morphological Operation using HDL coder
In this submission a basic image morphological operation called "Erosion" has been implemented using HDL coder.The implementation has been done using Gray scale image.The main motivation behind this work is to generate FPGA programmable bit file for programming the concerned FPGA board(in this case virtex-ML507 has been used).The generated vhdl code has been successfully simulated using ModelSim-10.1c and synthesized using Xilinx Virtex-ML507.In the synthesized system the clock frequency of 335.171 MHz has been achieved.
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SUMEET (2024). FPGA Implementation of the Gray Scale Image Erosion Morphological Operation using HDL coder (https://www.mathworks.com/matlabcentral/fileexchange/45532-fpga-implementation-of-the-gray-scale-image-erosion-morphological-operation-using-hdl-coder), MATLAB Central File Exchange. Récupéré le .
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- Code Generation >
- Image Processing and Computer Vision > Image Processing Toolbox >
- Code Generation > HDL Coder >
- FPGA, ASIC, and SoC Development > HDL Coder >
- Code Generation > HDL Verifier >
- FPGA, ASIC, and SoC Development > HDL Verifier >
- Image Processing and Computer Vision > Computer Vision Toolbox > Computer Vision Toolbox Supported Hardware >
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Version | Publié le | Notes de version | |
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1.1.0.0 | I have changed the title of the implementation for better access by the community. |
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1.0.0.0 |