HDL Coder Evaluation Reference Guide

Getting started guide for learning and evaluating HDL Coder
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Mise à jour 31 déc. 2023

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HDL-Coder-Evaluation-Reference-Guide

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Guidelines for getting started using HDL Coder to generate VHDL or Verilog to target FPGA or ASIC hardware. The document provides practical guidance for:

  • Setting up your MATLAB algorithm or Simulink model for HDL code generation
  • How to create HDL-ready Simulink models, Stateflow charts, and MATLAB Function blocks
  • Tips and advanced techniques for HDL code generation
  • Code generation settings for specific FPGA/SoC targets, including AXI interfaces
  • Converting to fixed-point or utilizing native floating-point
  • Optimizing for various goals and targets
  • Verifying your generated code

Examples are included to illustrate selected concepts.

Citation pour cette source

MathWorks HDL Coder Team (2024). HDL Coder Evaluation Reference Guide (https://github.com/mathworks/HDL-Coder-Evaluation-Reference-Guide/releases/tag/v4.0.0), GitHub. Récupéré le .

Compatibilité avec les versions de MATLAB
Créé avec R2023a
Compatible avec les versions R2023a à R2023b
Plateformes compatibles
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Version Publié le Notes de version
4.0.0

See release notes for this release on GitHub: https://github.com/mathworks/HDL-Coder-Evaluation-Reference-Guide/releases/tag/v4.0.0

3.0.0

See release notes for this release on GitHub: https://github.com/mathworks/HDL-Coder-Evaluation-Reference-Guide/releases/tag/v3.0.0

2.4.0.0

Updated for R2018b

2.3.0.0

Japanese translation of R2017b update

2.2.0.0

Updated to R2017b

2.1.0.0

Updated Japanese version for R2016b

2.0.0.0

Updated for R2016b

1.1.0.0

Added Japanese version of the guide

1.0.0.0

Pour consulter ou signaler des problèmes liés à ce module complémentaire GitHub, accédez au dépôt GitHub.
Pour consulter ou signaler des problèmes liés à ce module complémentaire GitHub, accédez au dépôt GitHub.