HDL Coder Support Package for Xilinx RFSoC Devices
Generate code for the FPGA portion of RFSoC devices
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Mise à jour
13 sept. 2023
This support package includes reference designs for popular RFSoC development kits, so you can generate HDL code and port mappings to I/O and AXI registers to interface with RF tiles and DDR memory, and interactively control the FPGA design from MATLAB.
You can use SoC Blockset for system-level modeling of RFSoC devices, configuration of custom RFSoC-based boards, and deployment of complete SoC applications, including executables for ARM Cortex-A53 processors.
For R2021a, to access the documentation for this support package, use the following commands in MATLAB:
>>cd(hdlcoder_rfsoc_doc_root)
>>open('hdlcoder_rfsoc_support_package_doc.pdf')
This support package is functional for R2021a up through R2023b. For R2024a and beyond, HDL Coder Support Package for Xilinx RFSoC Devices support is provided via HDL Coder Support Package for Xilinx FPGA and SoC Devices.
Compatibilité avec les versions de MATLAB
Créé avec
R2021a
Compatible avec les versions R2021a à R2023b
Plateformes compatibles
Windows macOS (Apple Silicon) macOS (Intel) LinuxCatégories
- Code Generation > HDL Coder >
- FPGA, ASIC, and SoC Development > HDL Coder >
- Code Generation > HDL Coder > HDL Coder Supported Hardware >
- FPGA, ASIC, and SoC Development > HDL Coder > HDL Coder Supported Hardware >
- Code Generation > HDL Coder > HDL Coder Supported Hardware > Xilinx FPGA and SoC Devices >
- FPGA, ASIC, and SoC Development > HDL Coder > HDL Coder Supported Hardware > Xilinx FPGA and SoC Devices >
En savoir plus sur HDL Coder dans Help Center et MATLAB Answers
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Remerciements
A inspiré : Avnet RFSoC Explorer Toolbox
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