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All filter coefficients not used in HDL code
coeff2 has been recognized as a power of 2, and so implemented using a shift. No multiply is needed for this operation.

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error input uint8 simulink
You can try using the <https://www.mathworks.com/help/dsp/ref/signalfromworkspace.html Signal From Workspace> block instead. I t...

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How do I modify dsp.HDLFFT generated RTL to create smaller FFTs?
Are you trying to reuse the code for variable length FFTs? If all you want is FFTs of different sizes, you can configure dsp.HD...

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Estimate execution time for a bloc simulink runing on FPGA
Please take a look at the <https://www.mathworks.com/help/simulink/slref/hdlcounter.html HDL Counter block> . The reset port can...

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How can i measure execution time or clock cycles utilized by a bloc simulink which will be run on FPGA" zedboard"?
If you have a valid in and valid out signals, or a similar protocol, you can plot these signals into the <https://www.mathworks....

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Can dsp.HDLFFT have controls on gate count, dimension and data width?
Current the HDL FFT does not support variable lengths. You can use the largest length needed (64K) and do bin mapping to run the...

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How do you pad zeros to a discrete element-based input?
If your input data is a frame, you can pad zeros and then use the To Sample block for the HDL input. If you are dealing with ...

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vision.BlobAnalysis to HDL
While there is no direct support for blob analysis, you can use Vision HDL Toolbox functionality to build your own blob analysis...

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CIC to HDL conversion
I suggest using the CIC Decimation block in Simulink. This should generate HDL code.

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how to optimize resource usage in HDL coder ?
You can share resources by using the Sharing option (right click on a subsystem to see the option). The number of registers seem...

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Why there is no sample time setting for HDL counter block ?
Unfortunately, it is not clear what the issue is. Can you provide a model and show where the hdl counter is? The registers in th...

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Cascade Filter in HDL Coder
If you doing this with Filter Design HDL Coder, please look at the pipeline options for multiplier pipelining, as well as the op...

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HDL coder: Display video output by controlling with switch
Could you show us the earlier part of the model (before the AND block) or perhaps attach the model itself?

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why the image filtering model generated from vision hdl toolbox create error when I try hdl workflow advisor saying that the "ctrl" input is a bus.. how should I solve this??
Could you please show an image of the failure? What workflow are you selecting in the HDL Workflow Advisor?

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How do i transfer an image pixel by pixel to zedoard-fpga using axi interface and process it and read the output back?
If all you are trying to do is to verify the functionality of your design, you can do so with <https://www.mathworks.com/example...

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HDL Coder atan / atan2
You can use the <https://www.mathworks.com/help/dsp/ref/complextomagnitudeanglehdloptimized.html Complex To Magnitude Angle bloc...

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HDL coder on image processing
You can use Vision HDL Toolbox blocks to design your system and generate HDL code. When you design this system, the inputs and o...

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double precision simulink hdlcoder support
HDL Coder supports code generation for a number of blocks in single precision. Please look at the following <https://www.mathwor...

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i am going to convert my m-file code into verilog or vhdl, but there are many errors regarding to the matlab commands, my code is based on image processing.
Please see if this <https://www.mathworks.com/examples/image/mw/images-ex51103367-generate-hdl-code-for-image-sharpening HDL exa...

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HDL coder simulation for video processing takes very long time. Is there way to do it faster ?
This is because of the pixel level processing. 480x640 translates to over 300K pixels per frame (not including blanking). Are yo...

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Relationship Between Simulink and FPGA Clock
HDL Coder generates as many clocks or clock enables as there are rates. So if you had a single rate model, you would have a sing...

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HDL coder Generated Model and Simulink Model Results Does not Match
You may be seeing the 0s inserted by the pipeline registers in the output. One way to debug is to have a parallel valid in - ...

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hdl code generation to come across check block compatibility error. How can I fix?
I assume you are trying to run this <https://www.mathworks.com/examples/simulink-hdl-coder/mw/hdlcoder_product-hdlcoder_sobel-ed...

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getting error while converting matlab code to verilog
Do you have any bit manipulation code? In that case, one guess is that the index you are passing needs to be between 1 and 9, wh...

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HDL coder Clocking Module
Please take a look at the <https://www.mathworks.com/help/hdlcoder/examples/using-multiple-clocks-in-hdl-coder.html#zmw57dd0e624...

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How do I debug Matlab NCO HDL Optimized in loop error?
The NCO block is unable to determine the data types of its inputs. Please put in a <https://www.mathworks.com/help/simulink/slre...

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HDL Coder: Replace the exp Function with a Lookup Table
You can try using a lookup table to implement exponent for a given input range. Another option is to try the <https://www.mathw...

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HDL Coder is not converting fft2 function
Please use the System object dsp.HDLFFT instead. There is an <https://www.mathworks.com/matlabcentral/answers/295481-why-do-i-ge...

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What are the steps to follow to Generate HDL Code from Matlab?
Take a look at the <https://www.mathworks.com/products/hdl-coder/code-examples.html tutorial section in the examples> for MATLAB...

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I am trying to convert the built in dsp.HDLIFFT function to HDL. When I get to the Fixed-Point Conversion step it states the inputs to the system object are not of the same type. How could I resolve this issue?
There are two changes you should make to the code. # Remove the assignment of double values to Yf. # Assuming that you want ...

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