Estimate execution time for a bloc simulink runing on FPGA

I use HDL Workflow to generate VHDL code of my bloc simulink. Now i need to estimate the execution time of my bloc when it run on FPGA. I have a solution which i could not apply. it consist to pass the input and output of my bloc simulink to a counter and use them to start and stop the counter. then we can retrieve the number of clock cycle between the input and output and multiply it by the frequency of FPGA. how can i do this ? any example for more understanding

Thank you for your help

Answer 1

[Bharath Venkataraman]

Please take a look at the HDL Counter block . The reset port can be your start and at the stop, you can either register the output of the counter or else hold enable low to prevent further counting.