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shauk
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Relationship Between Simulink and FPGA Clock

Asked by shauk
on 23 May 2017
Latest activity Commented on by David Amor on 21 Jul 2017
I am designing my model in Simulink and then download it to the FPGA using the HDL coder. My output has a Fs of 11.28 Mhz and my FPGA is running with a input clock of 22.56 MHz. So how does simulink make sure that my output from FPGA is also coming out at 11.28 MHz. Is it done by the clock bundles(clock enable, master clock and clock reset) signals that simulink adds to each block? Or do i need to do something else to make sure that my output signal at FPGA pin has a Fs of 11.28 MHz?

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2 Answers

Answer by David Amor on 23 May 2017
Edited by David Amor on 23 May 2017
 Accepted Answer

In the "Model Configuration Parameters" (the cog at the top) Set your solver to "Fixed-step" and "Discrete (no continuous states)" then choose the "Step Size" under additional options and type "1 / 22.56e6" (your sys clock).
Then your simulations will run at your system clock and you can confirm timings.

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thanks for the solution, just one more question, does the stop time in the simulation time bar matter? currently i set it to 10e6, i think this has a effect on calculating the step size
Stop time doesn't matter for fixed step size. The step size is not changed with the stop time.

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Answer by Bharath Venkataraman on 23 May 2017

HDL Coder generates as many clocks or clock enables as there are rates. So if you had a single rate model, you would have a single clock port which you could hook up to the 22.56 MHz clock. You can have a valid signal that toggles valid to give an effective rate of 11.28MHz.
If you truly want two raes, you will need to use either the rate transition or downsample block to model the functionality of how you are taking in data at 22.56MHz and sending out data at 11.28MHz. HDL Coder offers you an option to use a single clock with clock enables to represent the rates or two distinct clocks. Please look at this link to get further information.

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