Igor Freire
Universidade Federal do Pará
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Fpga-in-the-loop using IP core generation workflow with reference design?
Hi, Thanks for the information. These alternatives may be helpful at some point. However, I think the use that I was envision...
presque 9 ans il y a | 0
Question
Fpga-in-the-loop using IP core generation workflow with reference design?
Hi, I would like to generate a baseband processor IP using HDL coder and implement it on an FPGA connected to Simulink (in th...
presque 9 ans il y a | 2 réponses | 0
