John

Last seen: 3 jours il y a | Actif depuis 2025

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Using rate transition blocks in HDL coder
I'm not sure that the rate transition blocks are behaving as I am expecting them to when converting to HDL. For example if I hav...

12 jours il y a | 1 réponse | 0

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réponse

Question

HDL multi rate simulation
I'm having trouble understanding how to speed up the simulation when everything is running at the hardware rate. I have a clock ...

12 jours il y a | 1 réponse | 0

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réponse

Question

Mapping array to AXI4 slave
Does HDL coder handle the mapping of arrays differently than scalars? I created an output variable in stateflow that is size 32 ...

20 jours il y a | 1 réponse | 0

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réponse

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FPGA Data Capture in Custom Board
Is that a variable that should be declared within the plugin_rd() function? My HDL coder reference design uses a custom Qsys des...

environ 2 mois il y a | 0

Question

FPGA Data Capture in Custom Board
I have a custom cyclone v soc board. I'm trying to follow along with debug IP core using FPGA Data Capture. https://www.mathwork...

environ 2 mois il y a | 3 réponses | 0

3

réponses

Question

PMLSM Modeling cogging forces
Is there a way to modify the PMLSM Simscape block so that it accurately models cogging forces?

environ 2 mois il y a | 1 réponse | 0

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Question

FPGA in the loop Workflow
I need more help understanding the FPGA in the loop verification workflow. I have PMSM controller in Simulink that was converted...

environ 2 mois il y a | 1 réponse | 0

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Question

Connect AXI4 Master to multiple slaves
I defined an AXI4 Master Interface using the addAXI4MasterInterface method in my plugin_rd file. I want the master interface to ...

2 mois il y a | 1 réponse | 0

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Question

HDL Coder Error when converting AXI4 interface with different data rates
I'm having trouble understanding this error from HDL coder: Failed All the DUT ports connecting to the "f2h_sdram0 Read" interf...

3 mois il y a | 1 réponse | 0

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Question

AXI4 Master Read SDRAM
I'm using a Cyclone V SoC and in my reference design I have a FPGA to HPS SDRAM Interface enabled under the HPS. I'm expecting s...

4 mois il y a | 1 réponse | 0

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Question

Unable to fit HDL coder design into FPGA
I'm having trouble getting the HDL IP core generated by the HDL coder to fit in the FPGA I'm targeting (Cyclone V). I'm using th...

5 mois il y a | 1 réponse | 0

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Question

PMLSM Controller Over Active
I started with the three phase PMLSM example: https://www.mathworks.com/help/sps/ug/three-phase-pmlsm-drive.html . I modified th...

6 mois il y a | 1 réponse | 0

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Question

Specify the Location of custom IP cores in HDL Coder
I was following along with the instructions here: https://www.mathworks.com/help/hdlcoder/ug/define-and-add-ip-respository-to-cu...

10 mois il y a | 1 réponse | 0

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Question

HDL Coder with Custom IP Core
I was trying to add a custom IP core to my reference design and now when I run HDL workflow advisor using the hdl_led_blinking s...

10 mois il y a | 1 réponse | 0

1

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Question

Cannot find header file in Simulink Coder
I'm using the C Function block in Simulink to import custom C code into my model. Most of the standard C libraries I include Sim...

11 mois il y a | 2 réponses | 0

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réponses

Question

Read AXI4 address locations from Simulink
How can I read a particular address location from the AXI4 interface within Simulink HDL coder? For example, if I have a referen...

11 mois il y a | 1 réponse | 0

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Question

Build Linux Image for HDL Coder
I'm trying to follow along with the documentation here: https://www.mathworks.com/help/hdlcoder/ug/xilinx-zynq-linux-image-for-c...

11 mois il y a | 1 réponse | 0

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Question

Use Conduit Interface in HDL Coder
If I have a reference design that includes an IP core with a Conduit interface, how can I reference these signals in HDL coder? ...

12 mois il y a | 1 réponse | 0

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Question

HDL Coder Support Package for Intel FPGA and SoC Devices Setup
I am trying to go through the hardware setup for the HDL Coder Support Package for Intel FPGA and SoC Devices. I get to the step...

12 mois il y a | 1 réponse | 0

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Question

Specify clock pins in HDL Reference Design
I was reading over how to register a custom reference design: https://www.mathworks.com/help/hdlcoder/ug/register-a-custom-refer...

environ un an il y a | 1 réponse | 0

1

réponse