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Steven Zeng


Last seen: 6 mois il y a Actif depuis 2022

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Question


HDL code generation of delay block and problem in regard to the use of verilog ce_out
I'm building a PI contorller with HDL Coder, the model base rate is 80MHz, all blocks are defined with a sample rate of 16KHz. ...

environ 2 ans il y a | 1 réponse | 0

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