soukaina

Last seen: plus d'un an il y a | Actif depuis 2023

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Question

scalarize vector ports in generation vhdl code with hdl coder
I try to implement median filter in FPGA with matlab, but in the step ''verify with cosimulation" i got that error "vector port ...

plus d'un an il y a | 1 réponse | 0

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Question

implementation of median filtre on FPGA ?
Hi everyone, I want to design the median filter on FPGA. I got the output for median filter in matlab and also in matlab simulin...

plus d'un an il y a | 1 réponse | 0

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réponse