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Shashi TG


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Question


Problem with AXI stream interface in IP Integrator for Xilinx System generator IP cores
Hello there, I have system generator model which I have exported as an IP core to Vivado IP integrator. I have the AXI stream...

plus de 7 ans il y a | 1 réponse | 0

0

réponse

Réponse apportée
Garbage values when storing the data into .dat file
Hi thanks for reply. It throws me following error: <</matlabcentral/answers/uploaded_files/70897/mat.PNG>>

plus de 7 ans il y a | 0

Question


Garbage values when storing the data into .dat file
Hello there, I have a 3D array having data type float. When i store this array into a _.txt or .mat_ file and then open it, it ...

plus de 7 ans il y a | 3 réponses | 0

3

réponses

Question


Axi stream interface in Xilinx system generator
Hello there, I am trying to implement the AXI stream interface to an image negative operation in system generator. I want to v...

plus de 7 ans il y a | 1 réponse | 0

0

réponse

Question


Xilinx system generator Hardware co-simulation taking more time on FPGA
Hi there, I have a Xilinx system generator design which takes around 4 mins to run on a host PC. But when i do hardware cosim...

plus de 7 ans il y a | 1 réponse | 0

1

réponse

Question


Ragarding the custom IP core generation using xilinx system generator
Hi there, I have designed an up counter (counts from 0 to 10) using the system generator design flow. I exported the design ...

plus de 7 ans il y a | 1 réponse | 0

0

réponse

Question


Exporting Xilinx system generator design as IP catalog
Hi there, Can any type of xilinx system generator design be exported as an IP core to IP integrator? Or are there any conside...

plus de 7 ans il y a | 1 réponse | 0

1

réponse

Question


Random values output from the IP core
Hi all, I have an up counter (0-10) IP core generated from the Xilinx system generator. when I write an app in SDK and run t...

plus de 7 ans il y a | 1 réponse | 0

1

réponse

Question


No output for complex systen generator IP cores
Hello there, I am able to successfully generate IP cores for simple designs using IP integrator and get the output in SDK. But...

plus de 7 ans il y a | 1 réponse | 0

0

réponse

Question


How to use AXI stream interfaces in xilinx system generator?
HI there, I want know if AXI stream interfaces can be used in xilinx system generator model for a single input port? If yes, th...

plus de 7 ans il y a | 1 réponse | 0

1

réponse

Question


How can i perform imfreehand() operation in simulink?
Hi all, I need to draw a freehand ROI using the Simulink environment (equivalent to _imfreehand()_). How can I do that?

plus de 7 ans il y a | 1 réponse | 0

0

réponse

Question


Where can i get the following zip file ?
hdlcoderrecon_xsg_files_8a.zip

environ 8 ans il y a | 1 réponse | 0

0

réponse

Question


why there is an error while running the matlab documentation for HDL coder.?
I m compiling the documentation for HDL coder:"Image Reconstruction Using the MATLAB Function Block" . When i compile the entire...

environ 8 ans il y a | 1 réponse | 0

0

réponse

Question


How to find sum of all pixel value of ROI in a grayscale image?
I am trying to draw a ROI of a grayscale image using imfreehand. After drawing this, I want to count all the intensity levels co...

environ 8 ans il y a | 2 réponses | 0

2

réponses