HDL Verifier™ generates SystemVerilog DPI components from MATLAB^® functions and Simulink^® models for use during verification. If a verification team needs to access a component’s internal signals in order to debug from the testbench, the 2015b release introduces the ability to define internal signals as test points. These test points allow a team to access the testbench without having to bring the signals up through ports; instead, the signals are accessed via a DPI function call.