Processor-in-the-Loop Simulation

Test generated code on target processor or simulator

A processor-in-the-loop (PIL) simulation cross-compiles generated source code, and then downloads and runs object code on your target hardware. By comparing normal and PIL simulation results, you can test the numerical equivalence of your model and the generated code. During a PIL simulation, you can collect code coverage and execution-time metrics for the generated code.

A PIL simulation requires a connectivity configuration.

Apps

SIL/PIL Manager

Verify generated code

Packages

target Manage target hardware and build tool information

Classes

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PIL Connectivity – `target` API and rtIOStream API

`target.AddOn`	Describe add-on properties for target type
`target.API`	Describe API details
`target.APIImplementation`	Describe API implementation details
`target.Board`	Provide hardware board details
`target.BuildDependencies`	Describe C and C++ build dependencies to associate with target hardware
`target.CommunicationChannel`	Describe communication channel properties
`target.CommunicationInterface`	Describe data I/O details for target hardware
`target.CommunicationProtocolStack`	Describe communication protocol parameters
`target.Connection`	Base class for target connection properties
`target.ConnectionProperties`	Describe target-specific connection properties
`target.MainFunction`	Provide C and C++ dependencies for `main` function of target hardware application
`target.PILProtocol`	Describe PIL protocol implementation for target hardware
`target.Port`	Describe connection via target hardware port
`target.PortConnection`	Describe target connection port
`target.Processor`	Provide target processor information
`target.RS232Channel`	Describe serial communication channel
`target.TargetConnection`	Provide details about connecting MATLAB computer to target hardware
`target.TCPChannel`	Describe TCP communication properties
`target.Tools`	Describe properties of tools for target hardware
`target.UDPChannel`	Describe UDP communication

PIL Connectivity – `target` API and Debugger

`target.ApplicationStatus`	Describe status of application on target hardware
`target.Breakpoint`	Provide breakpoint details for debugger
`target.DebugExecutionTool`	Provide MATLAB service interface for debugger to manage processes on target hardware
`target.DebugIOTool`	Debug byte stream I/O tool service interface
`target.ExecutionService`	Describe implementation of execution service for target application
`target.ExecutionTool`	MATLAB service interface for tool that manages application execution on target hardware
`target.MATLABDependencies`	Describe MATLAB class and function dependencies

System Commands – `target` API

`target.ApplicationExecutionTool`	Capture system command information to run application from MATLAB computer
`target.Command`	Capture system command for execution on MATLAB computer
`target.HostProcessExecutionTool`	Capture system command information to run target application from MATLAB computer
`target.SystemCommandExecutionTool`	Capture system command information to run target application from MATLAB computer

Profiling – `target` API

`target.Function`	Provide function signature information
`target.Timer`	Provide timer details for processor

Objects

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PIL Connectivity – `rtw`

`rtw.connectivity.ComponentArgs`	Provide parameters for each target connectivity component
`rtw.connectivity.Config`	Define connectivity implementation that comprises builder, launcher, and communicator components
`rtw.connectivity.ConfigRegistry`	Register connectivity configuration
`rtw.connectivity.MakefileBuilder`	Configure toolchain-based build process
`rtw.connectivity.Launcher`	Control downloading, starting, and resetting of a target application
`rtw.connectivity.RtIOStreamHostCommunicator`	Configure development computer communications with target processor
`rtw.pil.RtIOStreamApplicationFramework`	Configure target-side communications

Functions

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rtIOStream API

`rtIOStreamClose`	Shut down communications channel
`rtIOStreamOpen`	Initialize communications channel
`rtIOStreamRecv`	Receive data through communication channel
`rtIOStreamSend`	Send data through communication channel

Connectivity Testing

`rtiostreamtest`	Test custom `rtiostream` interface implementation
`rtiostream_wrapper`	Test `rtiostream` shared library functions in MATLAB
`piltest`	Verify custom target connectivity configuration for Simulink PIL simulation

Topics

SIL and PIL Simulations
An overview of software-in-the-loop (SIL) and processor-in-the-loop simulations (PIL).
Choose a SIL or PIL Approach
Test code generated from top models, referenced models, or subsystems.
Create PIL Target Connectivity Configuration for Simulink
Customize PIL simulation for your target environment.
Host-Target Communication for Simulink PIL Simulation
Use the rtiostream API for communication between your development computer and target hardware during a PIL simulation.
Specify Hardware Timer for Simulink
Specify a hardware timer using the Code Replacement Tool.
Set Up PIL Connectivity by Using target Package
Provide PIL connectivity between Simulink^® and the target hardware.
Custom Toolchain Directives Required for Code Coverage and Execution Profiling
Specify compiler directives for building PIL application that supports code coverage analysis and execution profiling.
Configure and Run PIL Simulation
Set up and run top-model PIL, Model block PIL, and PIL block simulations.
Unit Test Subsystem Code with SIL/PIL Manager
Perform unit testing on atomic subsystem by using SIL/PIL Manager.
SIL/PIL Manager Verification Workflow
A simplified workflow for verifying generated code.
PIL Simulation Sequence
How a PIL simulation proceeds.
Simulation Mode Override Behavior in Model Reference Hierarchy
How the simulation mode of the top model or parent model determines the simulation behavior of a model hierarchy.
Field-Oriented Control of Permanent Magnet Synchronous Machine
Simulate motor control system, generate controller code, and use PIL simulation to test numerical equivalence and profile code execution times.
Security for PIL Simulations
Security measures for PIL simulations.
SIL and PIL Limitations
Modeling and code generation features that are not supported or partially supported by SIL and PIL simulations.