Complex Divide HDL Optimized

Divide one input by another and generate optimized HDL code

Since R2021a

• 

Libraries:
Fixed-Point Designer HDL Support / Math Operations

Description

The Complex Divide HDL Optimized block outputs the result of dividing the scalar num by the scalar den, such that y = num/den.

Examples

Implement Hardware-Efficient Complex Divide HDL Optimized

How to use the Complex Divide HDL Optimized block.

Open Live Script

Limitations

Data type override is not supported for the Complex Divide HDL Optimized block.

Ports

Input

num — Numerator

scalar

Numerator, specified as a scalar.

Slope-bias representation is not supported for fixed-point data types.

Data Types: single | double | fixed point
Complex Number Support: Yes

den — Denominator

scalar

Denominator, specified as a scalar.

Slope-bias representation is not supported for fixed-point data types.

Data Types: single | double | fixed point
Complex Number Support: Yes

validIn — Whether input is valid

Boolean scalar

Whether input is valid, specified as a Boolean scalar. This control signal indicates when the data from the num and den input ports are valid. When this value is 1 (true), the block captures the values at the input ports num and den. When this value is 0 (false), the block ignores the input samples.

Data Types: Boolean

Output

y — Output computed by dividing inputs

complex scalar

Output computed by dividing num by den, such that y = num/den, returned as a complex scalar with data type specified by Output datatype.

Data Types: single | double | fixed point

validOut — Whether output data is valid

Boolean scalar

Whether the output data is valid, returned as a Boolean scalar. When the value of this control signal is 1 (true), the block has successfully computed the output at port y. When this value is 0 (false), the output data is not valid.

Data Types: Boolean

Parameters

Output datatype — Data type of output

fixdt(1,18,10) (default) | single | fixdt(1,16,0) | <data type expression>

Data type of output y, specified as fixdt(1,18,10), single, fixdt(1,16,0), or as a user-specified data type expression. The type can be specified directly or expressed as a data type object, such as Simulink.NumericType.

Programmatic Use

Block Parameter: OutputType

Type: character vector

Values: 'fixdt(1,18,10)' | 'single' | 'fixdt(1,16,0)' | '<data type expression>'

Default: 'fixdt(1,18,10)'

Tips

The blocks Divide by Constant HDL Optimized, Real Divide HDL Optimized, and Complex Divide HDL Optimized all perform the division operation and generate optimized HDL code.

• Real Divide HDL Optimized and Complex Divide HDL Optimized are based on a CORIDC algorithm. These blocks accept a wide variety of inputs, but will result in greater latency.

• Divide by Constant HDL Optimized accepts only real inputs and a constant divisor. Use of this block consumes DSP slices, but will complete the division operation in fewer cycles and at a higher clock rate.

Algorithms

CORDIC

CORDIC is an acronym for COordinate Rotation DIgital Computer. The Givens rotation-based CORDIC algorithm is one of the most hardware-efficient algorithms available because it requires only iterative shift-add operations (see References). The CORDIC algorithm eliminates the need for explicit multipliers.

Fully Pipelined Fixed-Point Computations

The Complex Divide HDL Optimized block supports HDL code generation for fixed-point data with binary-point scaling. It is designed with this application in mind, and employs hardware specific semantics and optimizations. One of these optimizations is pipelining its entire internal circuitry to maintain a very high throughput.

When deploying intricate algorithms to FPGA or ASIC devices, there is often a trade-off between resource usage and total throughput for a given computation. Resource-sharing often reduces the resources consumed by a design, but also reduces the throughput in the process. Simple arithmetic and trigonometric computations, which typically form parts of bigger computations, require high throughput to drive circuits further in the design. Thus, fully pipelined implementations consume more on-chip resources but are beneficial in large designs.

All of the key computational units in the Complex Divide HDL Optimized block are fully pipelined internally. This includes not only the CORDIC circuitry used to perform the Givens rotations, but also the adders and shifters used elsewhere in the design, thus ensuring maximum throughput.

How to Interface with the Complex Divide HDL Optimized Block

Because of its fully pipelined nature, the Complex Divide HDL Optimized block is able to accept input data on any cycle, including consecutive cycles. To send input data to the block, the validIn signal must be set to true. When the block has finished the computation and is ready to send the output, it will set validOut to true for one clock cycle. For inputs sent on consecutive cycles, validOut will also be set to true on consecutive cycles. Both the numerator and the denominator must be sent together on the same cycle.

Division by Zero Behavior

For fixed-point inputs num and den, the Complex Divide HDL Optimized block saturates on overflow for division by zero. The behavior for fixed-point division by zero is summarized in the table below.

Wrap Overflow	Saturate Overflow
0/0 = 0	0/0 = 0
1/0 = 0	1/0 = upper bound
-1/0 = 0	-1/0 = lower bound

For floating-point inputs, the Complex Divide HDL Optimized block follows IEEE^® Standard 754.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

Slope-bias representation is not supported for fixed-point data types.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Restrictions

Supports binary-point scaled fixed-point data types only.

Version History

Introduced in R2021a