Divide

Compute division operation and simulate with latency

Since R2020b

• 

Libraries:
HDL Coder

Description

The Divide block performs the division operation on the input data signals. The block has control signals that indicate whether the input and output data are valid. You can also specify the number of iterations of the algorithm and the latency strategy.

To use this block in your Simulink^® model, open the HDLMathLib library by entering this command in the MATLAB^® Command Window:

open_system("HDLMathLib")

You can simulate the block with latency. For more information, see Latency Considerations.

Examples

Implement Divide Block with Control Signals

Implement the control-signal based Divide block and use it to generate HDL code.

• Open Script

Ports

Input

dividendDataIn — Dividend data signal

scalar | vector

Dividend input to calculate the division, specified as a scalar or vector.

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

divisorDataIn — Divisor data signal

scalar | vector

Divisor input to calculate the division, specified as a scalar or vector.

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

validIn — Whether input control signal is valid

scalar

Input control signal that indicates whether the input signal is valid, specified as a scalar.

Data Types: Boolean

Output

dataOut — Output data signal

scalar | vector

Output signal that is the division of the dividend and divisor input signals, returned as a scalar or vector.

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

validOut — Whether output control signal is valid

scalar

Output control signal that indicates whether output signal is valid, returned as a scalar.

Data Types: Boolean

Parameters

Latency strategy — Latency strategy

Max (default) | Min | Custom | Custom(PerIteration) | Zero

Specify whether to use minimum, maximum, custom, or zero latency. For more information, see Latency Strategy.

To use custom latency for the block, set the Latency strategy to Custom and enter the latency value in the Custom latency field.

You can also control the number of pipeline stages for the iterative algorithm. To customize the latency for iterative algorithm, set the Latency strategy to Custom(PerIteration) and enter the iterations per pipeline value in the IterationsPerPipeline field. (since R2025a)

Programmatic Use

Block Parameter: latencyMode

Type: character vector

Values: 'Max' | 'Min' | 'Custom' | 'Custom(PerIteration)' | 'Zero'

Default: 'Max'

Custom latency — Custom latency

0 (default) | positive integer

Specify the custom latency value. The latency must be a nonnegative integer in the range [0, L], where L is the maximum latency value of Divide block. For more information, see CustomLatency.

Dependency

To use this parameter, set Latency strategy to Custom.

Programmatic Use

Block Parameter: customLatencyValue

Type: Integer

Values: 0 to Max latency

Default: 0

IterationsPerPipeline — Iterations per pipeline

1 (default) | positive integer

Since R2025a

Specify the iterations to use per each pipeline stage in the algorithm.

Dependency

To enable this parameter, set Latency strategy to Custom(PerIteration).

Programmatic Use

Block Parameter: iterationsPerPipelineValue

Type: Integer

Values: Positive integer

Default: 1

Output data type — Output data type

Inherit: Inherit via internal rule (default) | Inherit: Same as first input | Inherit: Inherit via back propagation | Inherit: Keep MSB | Inherit: Match Scaling | int8 | uint8 | int16 | uint16 | int32 | uint32 | int64 | uint64 | fixdt(1,16) | fixdt(1,16,0) | <data type expression>

Specify the output data type. The data type can be inherited or specified directly.

Programmatic Use

Block Parameter: OutDataTypeStr

Type: character vector

Values: 'Inherit: Inherit via internal rule' | 'Inherit: Inherit via back propagation' | 'Inherit: Same as first input' | 'Inherit: Keep MSB' | 'Inherit: Match Scaling' | 'int8' | 'uint8' | int16 | 'uint16' | 'int32' | 'uint32' | 'int64' | 'uint64' | fixdt(1,16,0) | '<data type expression>'

Default: 'Inherit: Inherit via internal rule'

Integer rounding mode — Rounding mode for fixed-point operations

Zero (default) | Ceiling | Convergent | Floor | Nearest | Round | Simplest

Specify the rounding mode for fixed-point operations. For more information, see Rounding Modes.

Programmatic Use

Block Parameter: RndMeth

Type: character vector

Values: 'Zero' | 'Ceiling' | 'Convergent' | 'Floor' | 'Nearest' | 'ROund' | 'Simplest'

Default: 'Zero'

Algorithms

Latency Considerations

You can simulate the Divide block with latency. This block is a masked subsystem that contains the LumpLatency MATLAB Function block. The subsystem uses this MATLAB Function block to compute the latency based on the input and output data types. The software calculates the latency of the block using the word length and fractional length of fixed-point input and output.

To view the function that computes the latency of the block, open the LumpLatency block in the masked subsystem. To view inside the mask, click the ⇩ icon on the block.

This table shows how the block calculates the latency based on the setting of the Latency strategy parameter:

Latency Strategy	Latency Value (L)
Max	Uses maximum latency by using the equation L = N + 4, where N is the number of iterations. The software determines the value of N by using the fixed-point input and output data type, as described below.
Min	Uses minimum latency by using the equation L = 2 + ceil( N / 3).
Custom	Specifies a custom latency value. To specify the latency, enter a value between zero and the maximum latency in the Custom latency parameter. For more information, see Custom latency.
Custom(PerIteration)	Use this setting to control the pipeline stages for the iterative algorithm. Specify the number of pipeline stages per iteration using the IterationsPerPipeline parameter. The block uses the equation L = 2 + floor(N / K), where K is the value of the IterationsPerPipeline parameter.
Zero	The latency of the block is 0.

The software calculates the value of N using the signedness, word length and fractional length of the fixed-point input and output. To calculate N, the block follows these steps:

1. Check whether the output data type is a custom type. To determine whether the output data type is a custom type, these conditions must be true:

   • The value of max(DividendWL, DivisorWL) is not equal to OutputWL, where DividendWL is a dividend input word length, DivisorWL is a divisor input word length, and OutputWL is an output word length.

   • OutputFL is not equal to DividendFL -DivisorFL, where DividendFL is a dividend input fractional length, DivisorFL is a divisor input fractional length, and OutputFL is an output fractional length.

   • The value of the logical operation or(isOutputSignedXorInputSigned,isSignednessEqual) is 0. This logical expression gives the value of isOutputSignedXorInputSigned:

     isOutputSignedXorInputSigned = isOutputSigned and isXorInputSignedness

     where isOutputSigned evaluates to 1 when the output is signed and isXorInputSignedness evaluates 1 when the dividend and divisor inputs have different signedness.

     This logical expression gives the value of isSignednessEqual:

     isSignednessEqual = isInputSignednessEqual and isInputOutputSignEqual

     where isInputSignednessEqual evaluates to 1 when both inputs have the same signedness and isInputOutputSignEqual evaluates to 1 when the dividend data input and output have the same signedness.

2. Calculate the number of iterations based on custom output data type.

   • When the output data type is a custom type, this equation defines the iteration number N:

     N = max(DividendWL,DivisorWL) + abs(FractionDiff) + 1,

     where FractionDiff is a fractional difference given by this equation:

     FractionDiff = DividendFL - DivisorFL - OutputFL.

   • When the output data type is not a custom type, N is equal to the output word length.

3. Check the signedness of the divisor and dividend inputs. When the divisor and dividend inputs have different signedness, the software adds one more iteration to the number it calculates using step 2.

Pipeline Customization

The Divide block uses pipelined architectures to implement the iteration-based division algorithm. The number of iterations depends on the word length and fractional length of fixed-point input and output. The block performs a single iteration per pipeline stage and uses multiple pipeline stages for computation. A larger word length can provide higher resolution, but requires more iterations to process. By default, the block uses the maximum latency. For example, if your block requires the 20 iterations, the latency of the block is 24, based on the latency equation in Latency Considerations. When you require more iterations for processing the larger word length, the latency of the block also increases.

You can customize the latency for the iterative algorithm by setting Latency strategy to Custom(PerIteration), which allows you to control the number of iterations per pipeline stages. For example, if your block requires the 20 iterations and you want the block to perform the iterations in four pipeline stages, then set the IterationsPerPipeline to 20/4 = 5. By using the Custom(PerIteration) latency strategy, the latency of the block reduces to 6.

Extended Capabilities

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

The block supports HDL code generation using HDL Coder™. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

Architecture	Description
Module (default)	Generate code for the subsystem and the blocks within the subsystem.
BlackBox	Generate a black box interface. The generated HDL code includes only the input/output port definitions for the subsystem. Therefore, you can use a subsystem in your model to generate an interface to existing, manually written HDL code. The black-box interface generation for subsystems is similar to the Model block interface generation without the clock signals.
No HDL	Remove the subsystem from the generated code. You can use the subsystem in simulation, however, treat it as a “no-op” in the HDL code.

HDL Block Properties

General
AdaptivePipelining	Automatic pipeline insertion based on the synthesis tool, target frequency, and multiplier word-lengths. The default is inherit. See also AdaptivePipelining.
BalanceDelays	Detects introduction of new delays along one path and inserts matching delays on the other paths. The default is inherit. See also BalanceDelays.
ClockRatePipelining	Insert pipeline registers at a faster clock rate instead of the slower data rate. The default is inherit. See also ClockRatePipelining.
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline.
DistributedPipelining	Pipeline register distribution, or register retiming. The default is inherit. See also DistributedPipelining.
DSPStyle	Synthesis attributes for multiplier mapping. The default is none. See also DSPStyle.
FlattenHierarchy	Remove subsystem hierarchy from generated HDL code. The default is inherit. See also FlattenHierarchy.
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline.
SharingFactor	Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing.
StreamingFactor	Number of parallel data paths, or vectors, that are time multiplexed to transform into serial, scalar data paths. The default is 0, which implements fully parallel data paths. See also Streaming.

Target Specification

This block cannot be the DUT, so the block property settings in the Target Specification tab are ignored.

Limitations

• You cannot use this block in a Synchronous Subsystem block.

• The block does not support resource sharing optimization.

Version History

Introduced in R2020b

R2025a: Control number of pipeline stages per iteration

You can control the pipeline stages for iterative algorithms by setting the LatencyStrategy parameter HDL to Custom(PerIterations), then specifying the number of pipeline stages per iteration by using the IterationsPerPipeline parameter. Use this setting to control the pipeline stages in the generated code and optimize the design for speed and resource utilization.