In the HDL Coder™ block library, a subset of Simulink® blocks support floating-point library mapping. The subset includes:
Blocks that perform basic math operations such as addition, multiplication, and complex trigonometric sine and cosine functions. These blocks map to one or more floating-point IP units on the target FPGA device.
Discrete blocks, blocks that perform signal routing, and blocks that perform math operations such as matrix concatenation. These blocks need not map to a floating-point IP unit on the target FPGA device.
The following table summarizes the Simulink blocks that can map to FPGA floating-point IP cores.
When mapping to floating-point IP cores, some blocks have mode restrictions.
Some blocks do not map to a floating-point IP core in the third-party hardware. For example, the Abs block maps to an Altera® target IP core but not to a Xilinx® target IP core.
|Block||Altera Megafunction IP (ALTFP and ALTERA FP Functions)||Xilinx LogiCORE IP||Remarks and Limitations|
|Compare To Constant||✓||✓||—|
|Compare To Zero||✓||✓||—|
|Data Type Conversion||✓||✓|
|Decrement Real World||✓||✓||—|
|Discrete FIR Filter||✓||✓||—|
|Discrete Transfer Fcn||✓||✓||—|
|Product of Elements||✓||✓|
|Sum of Elements||✓||✓|
Following are the Simulink blocks that generate HDL code but need not map to an FPGA floating-point IP core.
Downsample (DSP System Toolbox)
Switch block with control input other
u2 ~= 0.
Upsample (DSP System Toolbox)
If your synthesis tool is Xilinx Vivado®, you cannot use FPGA floating-point library mapping.
Complex data types are not supported.
The streaming optimization is not supported with floating-point library mapping.
The resource sharing optimization is not supported with Unary Minus and Abs blocks.
For IP Core Generation, FPGA Turnkey, and Simulink Real-Time™ FPGA I/O workflows, your DUT ports cannot use floating-point data types.