Bus Selector

Select signals from incoming bus

• Library:

• Simulink / Commonly Used Blocks

  Simulink / Signal Routing

  HDL Coder / Signal Routing

Description

The Bus Selector block outputs a specified subset of the elements of the bus at its input. The block can output the specified elements as separate signals or as a new bus.

By default, Simulink^® implicitly converts a nonbus signal to a bus to support connecting the signal to a Bus Selector block. To prevent Simulink from performing that conversion, set the Non-bus signals treated as bus signals diagnostic to warning or error.

When the block outputs multiple elements, it outputs each element from a separate port from top to bottom of the block. See Port Location After Rotating or Flipping for a description of the port order for various block orientations.

In the Simulink Editor, as you draw a new signal line close to output side of a Bus Selector block and all output ports are already connected, Simulink Editor:

• Adds a port

• Prompts you to specify the signal to be selected

You cannot use this automatic port addition approach in either of these cases if:

• There is no bus input signal connected to the Bus Selector block.

• You do not specify a signal in response to the prompt that appears when you draw a signal line close to the Bus Selector block icon.

• You select the Output as virtual bus parameter.

Tip

For models that include buses composed of many elements, consider using the In Bus Element and Out Bus Element blocks. You can use these bus element port blocks instead of Inport with Bus Selector blocks for inputs, and Outport with Bus Creator blocks for outputs.

Bus element port blocks:

• Reduce signal line complexity and clutter in a block diagram.

• Make it easier to change the interface incrementally.

• Allow access to a bus element closer to the point of usage, avoiding the use of a Bus Selector and Goto block configuration.

Ports

Input

Port_1 — Input bus

real or complex values of any data type supported by Simulink except for arrays of buses

Input buses can have real or complex values of any data type supported by Simulink except for arrays of buses. To work with an array of buses, use a Selector block to select the index for the bus element that you want to use with the Bus Selector block. Then use that selected bus element with the Bus Selector block.

Output

Port_1 — Selected bus elements of input bus

standalone signal (default) | virtual bus | nonvirtual bus | array of buses

Selected bus elements of an input bus. For each output signal, this block uses a separate port from top to bottom of the block. See Port Location After Rotating or Flipping for a description of the port order for various block orientations.

If you select the Output as virtual bus parameter, the output bus is virtual. To produce nonvirtual bus output, insert a Signal Conversion block after the Bus Selector block. Set the Signal Conversion block Output parameter to Nonvirtual bus and use a Simulink.Bus bus object for the Data type parameter. For an example, see the Signal Conversion documentation.

Parameters

Signals in the bus — Element signals in input bus

list of signal names

List of bus element signals of the input bus, from which to select signals to output. To select a signal to output, click the signal in the list and then click Select.

To refresh the display to reflect modifications to the bus connected to the block, click Refresh.

To find the source of a signal entering the block, select the signal in the list and click Find. The Simulink software highlights the signal source in the block diagram.

Programmatic Use

Block Parameter: InputSignals

Type: matrix

Values: signal name

Default: {'[]'}

Filter by name — Filter set of displayed input signals by search term

text

Specify a search term to use for filtering a long list of input signals. Do not enclose the search term in quotation marks. The filter does a partial string search. To access filtering options, including using a regular expression to specify the search term, click the button on the right side of the Filter by name edit box.

Enable regular expression — Filter set of displayed input signals by regular expression

off (default) | on

Enable the use of MATLAB^® regular expressions for filtering signal names. For example, entering t$ in the Filter by name edit box displays all signals whose names end with a lowercase t (and their immediate parents). For details, see Regular Expressions (MATLAB).

Dependencies

To access this parameter, click the button on the right side of the Filter by name edit box.

Show filtered results as a flat list — Change appearance of filtered list

off (default) | on

By default, a tree displays the filtered signals, based on the search text in the Filter by name edit box. Select this parameter to use a flat list format that uses dot notation to reflect the hierarchy of buses.

Dependencies

To access this parameter, click the button on the right side of the Filter by name edit box

Selected signals — Selected bus elements

list of signal names

If an output signal listed in the Selected signals list box is not an input to the Bus Selector block, the signal name starts with three question marks (???).

You can change the list by using the Up, Down, and Remove buttons. To save your changes, click Apply. You can select multiple contiguous signals to move or remove. You cannot rearrange leaf signals within a bus. For example, you can move bus Bus1 up or down in the list, but you cannot reorder any of the bus elements of Bus1. Port connectivity is maintained when you change the signal order.

Programmatic Use

Block Parameter: OutputSignals

Type: character vector

Values: character vector in the form of 'signal1,signal2'

Default: none

Output as virtual bus — Output selected elements as bus

on (default) | off

By default, the block outputs the selected elements as standalone signals, each from an output port that is labeled with the corresponding bus element name. To output the selected bus element signals as a bus, select this parameter.

The output bus is virtual. To produce nonvirtual bus output, insert a Signal Conversion block after the Bus Selector block. Set the Signal Conversion block Output parameter to Nonvirtual bus and use a Simulink.Bus bus object for the Data type parameter. For an example, see the Signal Conversion documentation.

When the Selected signals list includes only one signal and you enable Output as virtual bus, then if the selected signal is:

• A nonbus signal, it is treated as a nonbus signal (it is not wrapped in a bus).

• A bus, then the output is that bus.

Programmatic Use

Block Parameter: OutputAsBus

Type: character vector

Values: 'on' | 'off'

Default: 'off'

Model Examples

Buses in Simulink

Introduces you to the following Simulink® bus signal capabilities: Bus Creator, Bus Selector, and Bus Assignment blocks

Open Model

Block Characteristics

Data Types	Boolean | bus | double | enumerated | fixed point | integer | single | string
Direct Feedthrough	yes
Multidimensional Signals	yes
Variable-Size Signals	yes
Zero-Crossing Detection	no

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

Actual data type or capability support depends on block implementation.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

To learn more about using buses for HDL code generation, see Buses (HDL Coder) and Use Bus Signals to Improve Readability of Model and Generate HDL Code (HDL Coder).

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion

Design and simulate fixed-point systems using Fixed-Point Designer™.

Actual data type or capability support depends on block implementation.