generatehdl

Generate HDL code for quantized filter

Description

example

generatehdl(filtSO,'InputDataType',nt) generates HDL code for the specified filter System object™ and the input data type, nt.

The generated file is a single source file that includes the entity declaration and architecture code. You can find this file in your current working folder, inside the hdlsrc subfolder.

generatehdl(filtSO,'InputDataType',nt,'FractionalDelayDataType',fd) generates HDL code for a dsp.VariableFractionalDelay filter System object. Specify the input data type, nt, and the fractional delay data type, fd.

generatehdl(filterObj) generates HDL code for the specified dfilt filter object using default settings.

example

generatehdl(___,Name,Value) uses optional name-value pair arguments, in addition to the input arguments in previous syntaxes. Use these properties to override default HDL code generation settings.

Examples

collapse all

Design a direct form symmetric equiripple filter with these specifications:

  • Normalized passband frequency of 0.2

  • Normalized stopband frequency of 0.22

  • Passband ripple of 1 dB

  • Stopband attenuation of 60 dB

The design function returns a dsp.FIRFilter System object™ that implements the specification.

filtSpecs = fdesign.lowpass('Fp,Fst,Ap,Ast',0.2,0.22,1,60);
FIRe = design(filtSpecs,'equiripple','FilterStructure','dfsymfir','SystemObject',true)
FIRe = 
  dsp.FIRFilter with properties:

            Structure: 'Direct form symmetric'
      NumeratorSource: 'Property'
            Numerator: [1x202 double]
    InitialConditions: 0

  Show all properties

To generate HDL code, call the generatehdl function. When the filter is a System object, you must specify a fixed-point data type for the input using the InputDataType property. The coder generates the file MyFilter.vhd in the default target folder, hdlsrc.

generatehdl(FIRe,'InputDataType',numerictype(1,16,15),'Name','MyFilter');
### Starting VHDL code generation process for filter: MyFilter
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex48836167/hdlsrc/MyFilter.vhd
### Starting generation of MyFilter VHDL entity
### Starting generation of MyFilter VHDL architecture
### Successful completion of VHDL code generation process for filter: MyFilter
### HDL latency is 2 samples

Design a direct form symmetric equiripple filter with these specifications:

  • Normalized passband frequency of 0.2

  • Normalized stopband frequency of 0.22

  • Passband ripple of 1 dB

  • Stopband attenuation of 60 dB

The design function returns a dsp.FIRFilter System object™ that implements the specification.

filtSpecs = fdesign.lowpass('Fp,Fst,Ap,Ast',0.2,0.22,1,60);
FIRe = design(filtSpecs,'equiripple','FilterStructure','dfsymfir','SystemObject',true)
FIRe = 
  dsp.FIRFilter with properties:

            Structure: 'Direct form symmetric'
      NumeratorSource: 'Property'
            Numerator: [1x202 double]
    InitialConditions: 0

  Show all properties

Generate VHDL code and a VHDL test bench for the FIR equiripple filter. When the filter is a System object, you must specify a fixed-point data type for the input data type. The coder generates the files MyFilter.vhd and MyFilterTB.vhd in the default target folder, hdlsrc.

generatehdl(FIRe,'InputDataType',numerictype(1,16,15),'Name','MyFilter',...
    'GenerateHDLTestbench','on','TestBenchName','MyFilterTB')
### Starting VHDL code generation process for filter: MyFilter
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex63281302/hdlsrc/MyFilter.vhd
### Starting generation of MyFilter VHDL entity
### Starting generation of MyFilter VHDL architecture
### Successful completion of VHDL code generation process for filter: MyFilter
### HDL latency is 2 samples
### Starting generation of VHDL Test Bench.
### Generating input stimulus
### Done generating input stimulus; length 4486 samples.
### Generating Test bench: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex63281302/hdlsrc/MyFilterTB.vhd
### Creating stimulus vectors ...
### Done generating VHDL Test Bench.

Design a direct form symmetric equiripple filter with fully parallel (default) architecture and programmable coefficients. The design function returns a dsp.FIRFilter System object™ with default lowpass filter specification.

firfilt = design(fdesign.lowpass,'equiripple','FilterStructure','dfsymfir','SystemObject',true)
firfilt = 
  dsp.FIRFilter with properties:

            Structure: 'Direct form symmetric'
      NumeratorSource: 'Property'
            Numerator: [1x43 double]
    InitialConditions: 0

  Show all properties

To generate HDL code, call the generatehdl function. When the filter is a System object, you must specify a fixed-point data type for the input data. To generate a processor interface for the coefficients, you must specify an additional name-value pair argument.

generatehdl(firfilt,'InputDataType',numerictype(1,16,15),'CoefficientSource','ProcessorInterface')
### Starting VHDL code generation process for filter: firfilt
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex74213987/hdlsrc/firfilt.vhd
### Starting generation of firfilt VHDL entity
### Starting generation of firfilt VHDL architecture
### Successful completion of VHDL code generation process for filter: firfilt
### HDL latency is 2 samples

The coder generates this VHDL entity for the filter object.

Create a direct form antisymmetric filter with coefficients:

coeffs = fir1(22,0.45);
firfilt = dsp.FIRFilter('Numerator',coeffs,'Structure','Direct form antisymmetric')
firfilt = 
  dsp.FIRFilter with properties:

            Structure: 'Direct form antisymmetric'
      NumeratorSource: 'Property'
            Numerator: [1x23 double]
    InitialConditions: 0

  Show all properties

To generate HDL code, call the generatehdl function. When the filter is a System object, you must specify a fixed-point data type for the input data. To generate a partly serial architecture, specify a serial partition. To enable CoefficientMemory property, you must set CoefficientSource to ProcessorInterface.

generatehdl(firfilt,'InputDataType',numerictype(1,16,15), ...
    'SerialPartition',[7 4],'CoefficientMemory','DualPortRAMs', ...
    'CoefficientSource','ProcessorInterface')
### Starting VHDL code generation process for filter: firfilt
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex21465785/hdlsrc/firfilt.vhd
### Starting generation of firfilt VHDL entity
### Starting generation of firfilt VHDL architecture
### Clock rate is 7 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: firfilt
### HDL latency is 3 samples

The generated code includes a dual-port RAM interface for the programmable coefficients.

Explore clock rate and latency for different serial implementations of the same filter. Using a symmetric structure also allows the filter logic to share multipliers for symmetric coefficients.

Create a direct form symmetric FIR filter with these specifications:

  • Filter order 13

  • Normalized cut-off frequency of 0.4 for the 6-dB point

The design function returns a dsp.FIRFilter System object™ that implements the specification.

FIR = design(fdesign.lowpass('N,Fc',13,.4),'FilterStructure','dfsymfir','SystemObject',true)
FIR = 
  dsp.FIRFilter with properties:

            Structure: 'Direct form symmetric'
      NumeratorSource: 'Property'
            Numerator: [1x14 double]
    InitialConditions: 0

  Show all properties

To generate HDL code, call the generatehdl function. When the filter is a System object, you must specify a fixed-point data type for the input data.

For a baseline comparison, first generate a default fully parallel architecture.

generatehdl(FIR,'Name','FullyParallel', ...
    'InputDataType',numerictype(1,16,15))
### Starting VHDL code generation process for filter: FullyParallel
### Generating: /tmp/Bdoc19b_1192687_40257/tp06f2f641/hdlfilter-ex94948885/hdlsrc/FullyParallel.vhd
### Starting generation of FullyParallel VHDL entity
### Starting generation of FullyParallel VHDL architecture
### Successful completion of VHDL code generation process for filter: FullyParallel
### HDL latency is 2 samples

Generate a fully serial architecture by setting the partition size to the effective filter length. The system clock rate is six times the input sample rate. The reported HDL latency is one sample greater than the default parallel implementation.

generatehdl(FIR,'SerialPartition',6,'Name','FullySerial', ...
    'InputDataType',numerictype(1,16,15))
### Starting VHDL code generation process for filter: FullySerial
### Generating: /tmp/Bdoc19b_1192687_40257/tp06f2f641/hdlfilter-ex94948885/hdlsrc/FullySerial.vhd
### Starting generation of FullySerial VHDL entity
### Starting generation of FullySerial VHDL architecture
### Clock rate is 6 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: FullySerial
### HDL latency is 3 samples

Generate a partly serial architecture with three equal partitions. This architecture uses three multipliers. The clock rate is two times the input rate, and the latency is the same as the default parallel implementation.

generatehdl(FIR,'SerialPartition',[2 2 2],'Name','PartlySerial', ...
    'InputDataType',numerictype(1,16,15))
### Starting VHDL code generation process for filter: PartlySerial
### Generating: /tmp/Bdoc19b_1192687_40257/tp06f2f641/hdlfilter-ex94948885/hdlsrc/PartlySerial.vhd
### Starting generation of PartlySerial VHDL entity
### Starting generation of PartlySerial VHDL architecture
### Clock rate is 2 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: PartlySerial
### HDL latency is 3 samples

Generate a cascade-serial architecture by enabling accumulator reuse. Specify the three partitions in descending order of size. Notice that the clock rate is higher than the rate in the partly serial (without accumulator reuse) example.

generatehdl(FIR,'SerialPartition',[3 2 1],'ReuseAccum','on','Name','CascadeSerial', ...
    'InputDataType',numerictype(1,16,15))
### Starting VHDL code generation process for filter: CascadeSerial
### Generating: /tmp/Bdoc19b_1192687_40257/tp06f2f641/hdlfilter-ex94948885/hdlsrc/CascadeSerial.vhd
### Starting generation of CascadeSerial VHDL entity
### Starting generation of CascadeSerial VHDL architecture
### Clock rate is 4 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: CascadeSerial
### HDL latency is 3 samples

You can also generate a cascade-serial architecture without specifying the partitions explicitly. The coder automatically selects partition sizes.

generatehdl(FIR,'ReuseAccum','on','Name','CascadeSerial', ...
    'InputDataType',numerictype(1,16,15))
### Starting VHDL code generation process for filter: CascadeSerial
### Generating: /tmp/Bdoc19b_1192687_40257/tp06f2f641/hdlfilter-ex94948885/hdlsrc/CascadeSerial.vhd
### Starting generation of CascadeSerial VHDL entity
### Starting generation of CascadeSerial VHDL architecture
### Clock rate is 4 times the input sample rate for this architecture.
### Serial partition # 1 has 3 inputs.
### Serial partition # 2 has 3 inputs.
### Successful completion of VHDL code generation process for filter: CascadeSerial
### HDL latency is 3 samples

Create a two-stage cascaded filter with these specifications for each filter stage:

  • Direct form symmetric FIR filter

  • Filter order 8

  • Normalized cut-off frequency of 0.4 for the 6-dB point

Each call of the design function returns a dsp.FIRFilter System object™ that implements the specification. The cascade function returns a two-stage cascaded filter.

lp = design(fdesign.lowpass('N,Fc',8,.4),'FilterStructure','dfsymfir','SystemObject',true)
lp = 
  dsp.FIRFilter with properties:

            Structure: 'Direct form symmetric'
      NumeratorSource: 'Property'
            Numerator: [1x9 double]
    InitialConditions: 0

  Show all properties

hp = design(fdesign.highpass('N,Fc',8,.4),'FilterStructure','dfsymfir','SystemObject',true)
hp = 
  dsp.FIRFilter with properties:

            Structure: 'Direct form symmetric'
      NumeratorSource: 'Property'
            Numerator: [1x9 double]
    InitialConditions: 0

  Show all properties

casc = cascade(lp,hp)
casc = 
  dsp.FilterCascade with properties:

    Stage1: [1x1 dsp.FIRFilter]
    Stage2: [1x1 dsp.FIRFilter]

To generate HDL code, call the generatehdl function for the cascaded filter. When the filter is a System object, you must specify a fixed-point data type for the input data.

Specify different partitions for each cascade stage as a cell array.

generatehdl(casc,'InputDataType',numerictype(1,16,15),'SerialPartition',{[3 2],[4 1]})
### Starting VHDL code generation process for filter: casfilt
### Cascade stage # 1
### Starting VHDL code generation process for filter: casfilt_stage1
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex16715237/hdlsrc/casfilt_stage1.vhd
### Starting generation of casfilt_stage1 VHDL entity
### Starting generation of casfilt_stage1 VHDL architecture
### Clock rate is 3 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: casfilt_stage1
### Cascade stage # 2
### Starting VHDL code generation process for filter: casfilt_stage2
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex16715237/hdlsrc/casfilt_stage2.vhd
### Starting generation of casfilt_stage2 VHDL entity
### Starting generation of casfilt_stage2 VHDL architecture
### Clock rate is 4 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: casfilt_stage2
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex16715237/hdlsrc/casfilt.vhd
### Starting generation of casfilt VHDL entity
### Starting generation of casfilt VHDL architecture
### Successful completion of VHDL code generation process for filter: casfilt
### HDL latency is 2 samples

To explore the effective filter length and partitioning options for each filter stage of a cascade, call the hdlfilterserialinfo function. The function returns a partition vector corresponding to a desired number of multipliers. Request serial partition possibilities for the first stage, and choose a number of multipliers.

hdlfilterserialinfo(casc.Stage1,'InputDataType',numerictype(1,16,15))
   | Total Coefficients | Zeros | A/Symm | Effective |
   ---------------------------------------------------
   |          9         |   0   |    4   |     5     |

Effective filter length for SerialPartition value is 5.

  Table of 'SerialPartition' values with corresponding values of 
  folding factor and number of multipliers for the given filter.

   | Folding Factor | Multipliers | SerialPartition |
   --------------------------------------------------
   |        1       |      5      |[1 1 1 1 1]      |
   |        2       |      3      |[2 2 1]          |
   |        3       |      2      |[3 2]            |
   |        4       |      2      |[4 1]            |
   |        5       |      1      |[5]              |

Select a serial partition vector for a target of two multipliers, and pass the vectors to the generatehdl function. Calling the function this way returns the first possible partition vector, but there are multiple partition vectors that achieve a two-multiplier architecture. Each stage uses a different clock rate based on the number of multipliers. The coder generates a timing controller to derive these clocks.

sp1 = hdlfilterserialinfo(casc.Stage1,'InputDataType',numerictype(1,16,15),'Multiplier',2)
sp1 = 1×2

     3     2

sp2 = hdlfilterserialinfo(casc.Stage2,'InputDataType',numerictype(1,16,15),'Multiplier',3)
sp2 = 1×3

     2     2     1

generatehdl(casc,'InputDataType',numerictype(1,16,15),'SerialPartition',{sp1,sp2})
### Starting VHDL code generation process for filter: casfilt
### Cascade stage # 1
### Starting VHDL code generation process for filter: casfilt_stage1
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex16715237/hdlsrc/casfilt_stage1.vhd
### Starting generation of casfilt_stage1 VHDL entity
### Starting generation of casfilt_stage1 VHDL architecture
### Clock rate is 3 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: casfilt_stage1
### Cascade stage # 2
### Starting VHDL code generation process for filter: casfilt_stage2
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex16715237/hdlsrc/casfilt_stage2.vhd
### Starting generation of casfilt_stage2 VHDL entity
### Starting generation of casfilt_stage2 VHDL architecture
### Clock rate is 2 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: casfilt_stage2
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex16715237/hdlsrc/casfilt.vhd
### Starting generation of casfilt VHDL entity
### Starting generation of casfilt VHDL architecture
### Successful completion of VHDL code generation process for filter: casfilt
### HDL latency is 2 samples

Create a direct form I SOS filter with these specifications:

  • Sampling frequency of 48 kHz

  • Filter order 5

  • Cut-off frequency of 10.8 kHz for the 3 dB point

The design function returns a dsp.BiquadFilter System object™ that implements the specification. The custom accumulator data type avoids quantization error.

Fs = 48e3;
Fc = 10.8e3;
N = 5;
lp = design(fdesign.lowpass('n,f3db',N,Fc,Fs),'butter', ...
    'FilterStructure','df1sos','SystemObject',true) 
lp = 
  dsp.BiquadFilter with properties:

                       Structure: 'Direct form I'
                 SOSMatrixSource: 'Property'
                       SOSMatrix: [3x6 double]
                     ScaleValues: [4x1 double]
      NumeratorInitialConditions: 0
    DenominatorInitialConditions: 0
        OptimizeUnityScaleValues: true

  Show all properties

nt_accum = numerictype('Signedness','auto','WordLength',20, ...
    'FractionLength',15);
nt_input = numerictype(1,16,15);
lp.NumeratorAccumulatorDataType = 'Custom';
lp.CustomNumeratorAccumulatorDataType = nt_accum;
lp.DenominatorAccumulatorDataType = 'Custom';
lp.CustomDenominatorAccumulatorDataType = nt_accum;

To list all possible serial architecture specifications for this filter, call the hdlfilterserialinfo function. When the filter is a System object, you must specify a fixed-point data type for the input data.

hdlfilterserialinfo(lp,'InputDataType',nt_input)
  Table of folding factors with corresponding number of multipliers for the given filter.

   | Folding factor | Multipliers |
   --------------------------------
   |        6       |      3      |
   |        9       |      2      |
   |       18       |      1      |

To generate HDL code, call the generatehdl function with one of the serial architectures. Specify either the NumMultipliers or FoldingFactor property, but not both. For instance, using the NumMultipliers property:

generatehdl(lp,'NumMultipliers',2,'InputDataType',nt_input)
### Starting VHDL code generation process for filter: lp
### Generating: /tmp/Bdoc19b_1192687_40257/tp06f2f641/hdlfilter-ex90334139/hdlsrc/lp.vhd
### Starting generation of lp VHDL entity
### Starting generation of lp VHDL architecture
### Successful completion of VHDL code generation process for filter: lp
### HDL latency is 2 samples

Alternatively, specify the same architecture with the FoldingFactor property.

generatehdl(lp,'FoldingFactor',9,'InputDataType',nt_input)
### Starting VHDL code generation process for filter: lp
### Generating: /tmp/Bdoc19b_1192687_40257/tp06f2f641/hdlfilter-ex90334139/hdlsrc/lp.vhd
### Starting generation of lp VHDL entity
### Starting generation of lp VHDL architecture
### Successful completion of VHDL code generation process for filter: lp
### HDL latency is 2 samples

Both these commands generate a filter that uses a total of two multipliers, with a latency of nine clock cycles. This architecture uses less area than the parallel implementation, at the expense of latency.

Use distributed arithmetic options to reduce the number of multipliers in the filter implementation.

Create a direct-form FIR filter and calculate the filter length, FL.

filtdes = fdesign.lowpass('N,Fc,Ap,Ast',30,0.4,0.05,0.03,'linear');
firfilt = design(filtdes,'FilterStructure','dffir','SystemObject',true);
FL = length(find(firfilt.Numerator ~= 0))
FL = 31

Specify a set of partitions such that the partition sizes add up to the filter length. This is just one partition option, you can specify other combinations of sizes.

generatehdl(firfilt,'InputDataType',numerictype(1,16,15), ...
    'DALUTPartition',[8 8 8 7])
Warning: Structure fir has symmetric coefficients, consider converting to structure symmetricfir for reduced area.
Warning: Structure fir has symmetric coefficients, consider converting to structure symmetricfir for reduced area.
### Starting VHDL code generation process for filter: firfilt
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex00198568/hdlsrc/firfilt.vhd
### Starting generation of firfilt VHDL entity
### Starting generation of firfilt VHDL architecture
### Clock rate is 16 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: firfilt
### HDL latency is 3 samples

For comparison, create a direct-form symmetric FIR filter. The filter length is smaller in the symmetric case.

filtdes = fdesign.lowpass('N,Fc,Ap,Ast',30,0.4,0.05,0.03,'linear');
firfilt = design(filtdes,'FilterStructure','dfsymfir','SystemObject',true);
FL = ceil(length(find(firfilt.Numerator ~= 0))/2)
FL = 16

Specify a set of partitions such that the partition sizes add up to the filter length. This is just one partition option, you can specify other combinations of sizes. Tip: Use the hdlfilterdainfo function to display the effective filter length, LUT partitioning options, and possible DARadix values for a filter.

generatehdl(firfilt,'InputDataType',numerictype(1,16,15), ...
    'DALUTPartition',[8 8])
### Starting VHDL code generation process for filter: firfilt
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex00198568/hdlsrc/firfilt.vhd
### Starting generation of firfilt VHDL entity
### Starting generation of firfilt VHDL architecture
### Clock rate is 17 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: firfilt
### HDL latency is 3 samples

Use distributed arithmetic options to reduce the number of multipliers in the filter implementation.

Create a direct-form FIR polyphase decimator, and calculate the filter length.

d = fdesign.decimator(4);
filt = design(d,'SystemObject',true);
FL = size(polyphase(filt),2)
FL = 27

Specify distributed arithmetic LUT partitions that add up to the filter size. When you specify partitions as a vector for a polyphase filter, each subfilter uses the same partitions.

generatehdl(filt,'InputDataType',numerictype(1,16,15), ...
    'DALUTPartition',[8 8 8 3])
### Starting VHDL code generation process for filter: firdecim
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex51670151/hdlsrc/firdecim.vhd
### Starting generation of firdecim VHDL entity
### Starting generation of firdecim VHDL architecture
### Clock rate is 4 times the input and 16 times the output sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: firdecim
### HDL latency is 16 samples

You can also specify unique partitions for each subfilter. For the same filter, specify subfilter partitioning as a matrix. The length of the first subfilter is 1, and the other subfilters have length 26. Tip: Use the hdlfilterdainfo function to display the effective filter length, LUT partitioning options, and possible DARadix values for a filter.

d = fdesign.decimator(4);
filt = design(d,'SystemObject',true);
generatehdl(filt,'InputDataType',numerictype(1,16,15), ...
    'DALUTPartition',[1 0 0 0; 8 8 8 2; 8 8 6 4; 8 8 8 2])
### Starting VHDL code generation process for filter: firdecim
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex51670151/hdlsrc/firdecim.vhd
### Starting generation of firdecim VHDL entity
### Starting generation of firdecim VHDL architecture
### Clock rate is 4 times the input and 16 times the output sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: firdecim
### HDL latency is 16 samples

Use distributed arithmetic options to reduce the number of multipliers in the filter implementation.

Create Cascaded Filter

Create a two-stage cascaded filter. Define different LUT partitions for each stage, and specify the partition vectors in a cell array.

lp = design(fdesign.lowpass('N,Fc',8,.4),'filterstructure','dfsymfir', ...
    'SystemObject',true);
hp = design(fdesign.highpass('N,Fc',8,.4),'filterstructure','dfsymfir', ...
    'SystemObject',true);
casc = cascade(lp,hp);
nt1 = numerictype(1,12,10);
generatehdl(casc,'InputDataType',nt1,'DALUTPartition',{[3 2],[2 2 1]})
### Starting VHDL code generation process for filter: casfilt
### Cascade stage # 1
### Starting VHDL code generation process for filter: casfilt_stage1
### Generating: \\fs-21-ah\home$\bvenkata\Documents\MATLAB\Examples\hdlfilter-ex17169310\hdlsrc\casfilt_stage1.vhd
### Starting generation of casfilt_stage1 VHDL entity
### Starting generation of casfilt_stage1 VHDL architecture
### Clock rate is 13 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: casfilt_stage1
### Cascade stage # 2
### Starting VHDL code generation process for filter: casfilt_stage2
### Generating: \\fs-21-ah\home$\bvenkata\Documents\MATLAB\Examples\hdlfilter-ex17169310\hdlsrc\casfilt_stage2.vhd
### Starting generation of casfilt_stage2 VHDL entity
### Starting generation of casfilt_stage2 VHDL architecture
### Clock rate is 29 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: casfilt_stage2
### Generating: \\fs-21-ah\home$\bvenkata\Documents\MATLAB\Examples\hdlfilter-ex17169310\hdlsrc\casfilt.vhd
### Starting generation of casfilt VHDL entity
### Starting generation of casfilt VHDL architecture
### Successful completion of VHDL code generation process for filter: casfilt
### HDL latency is 4 samples

Distributed Arithmetic Options

Use the hdlfilterdainfo function to display the effective filter length, LUT partitioning options, and possible DARadix values for each filter stage of a cascade. The function returns a LUT partition vector corresponding to a desired number of address bits.

Request LUT partition possibilities for the first stage.

 hdlfilterdainfo(casc.Stage1,'InputDataType',nt1);
   | Total Coefficients | Zeros | A/Symm | Effective |
   ---------------------------------------------------
   |          9         |   0   |    4   |     5     |

Effective filter length for SerialPartition value is 5.

  Table of 'DARadix' values with corresponding values of 
  folding factor and multiple for LUT sets for the given filter.

   | Folding Factor | LUT-Sets Multiple | DARadix |
   ------------------------------------------------
   |        1       |         12        |   2^12  |
   |        3       |         6         |   2^6   |
   |        4       |         4         |   2^4   |
   |        5       |         3         |   2^3   |
   |        7       |         2         |   2^2   |
   |       13       |         1         |   2^1   |

  Details of LUTs with corresponding 'DALUTPartition' values.

   | Max Address Width | Size(bits) |      LUT Details      | DALUTPartition |
   ---------------------------------------------------------------------------
   |         5         |     416    |1x32x13                |[5]             |
   |         4         |     216    |1x16x12, 1x2x12        |[4 1]           |
   |         3         |     124    |1x4x13, 1x8x9          |[3 2]           |
   |         2         |     104    |1x2x12, 1x4x12, 1x4x8  |[2 2 1]         |

Notes:
1. LUT Details indicates number of LUTs with their sizes. e.g. 1x1024x18
   implies 1 LUT of 1024 18-bit wide locations.

To request LUT partition possibilities for the second stage, you must first determine the input data type of the second stage.

y = casc.Stage1(fi(0,nt1));
nt2 = y.numerictype;
hdlfilterdainfo(casc.Stage2,'InputDataType',nt2);
   | Total Coefficients | Zeros | A/Symm | Effective |
   ---------------------------------------------------
   |          9         |   0   |    4   |     5     |

Effective filter length for SerialPartition value is 5.

  Table of 'DARadix' values with corresponding values of 
  folding factor and multiple for LUT sets for the given filter.

   | Folding Factor | LUT-Sets Multiple | DARadix |
   ------------------------------------------------
   |        1       |         28        |   2^28  |
   |        3       |         14        |   2^14  |
   |        5       |         7         |   2^7   |
   |        8       |         4         |   2^4   |
   |       15       |         2         |   2^2   |
   |       29       |         1         |   2^1   |

  Details of LUTs with corresponding 'DALUTPartition' values.

   | Max Address Width | Size(bits) |       LUT Details      | DALUTPartition |
   ----------------------------------------------------------------------------
   |         5         |     896    |1x32x28                 |[5]             |
   |         4         |     488    |1x16x27, 1x2x28         |[4 1]           |
   |         3         |     304    |1x4x28, 1x8x24          |[3 2]           |
   |         2         |     256    |1x2x28, 1x4x23, 1x4x27  |[2 2 1]         |

Notes:
1. LUT Details indicates number of LUTs with their sizes. e.g. 1x1024x18
   implies 1 LUT of 1024 18-bit wide locations.

Different LUT Partitions for Each Stage

Select address widths and folding factors to obtain LUT partition for each stage. The first stage uses LUTs with a maximum address size of five bits. The second stage uses LUTs with a maximum address size of three bits. They run at the same clock rate, and have different LUT partitions.

dp1 = hdlfilterdainfo(casc.Stage1,'InputDataType',nt1, ...
    'LUTInputs',5,'FoldingFactor',3);
dp2 = hdlfilterdainfo(casc.Stage2,'InputDataType',nt1, ...
    'LUTInputs',3,'FoldingFactor',5);
generatehdl(casc,'InputDataType',nt1,'DALUTPartition',{dp1,dp2});
### Starting VHDL code generation process for filter: casfilt
### Cascade stage # 1
### Starting VHDL code generation process for filter: casfilt_stage1
### Generating: \\fs-21-ah\home$\bvenkata\Documents\MATLAB\Examples\hdlfilter-ex17169310\hdlsrc\casfilt_stage1.vhd
### Starting generation of casfilt_stage1 VHDL entity
### Starting generation of casfilt_stage1 VHDL architecture
### Clock rate is 13 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: casfilt_stage1
### Cascade stage # 2
### Starting VHDL code generation process for filter: casfilt_stage2
### Generating: \\fs-21-ah\home$\bvenkata\Documents\MATLAB\Examples\hdlfilter-ex17169310\hdlsrc\casfilt_stage2.vhd
### Starting generation of casfilt_stage2 VHDL entity
### Starting generation of casfilt_stage2 VHDL architecture
### Clock rate is 29 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: casfilt_stage2
### Generating: \\fs-21-ah\home$\bvenkata\Documents\MATLAB\Examples\hdlfilter-ex17169310\hdlsrc\casfilt.vhd
### Starting generation of casfilt VHDL entity
### Starting generation of casfilt VHDL architecture
### Successful completion of VHDL code generation process for filter: casfilt
### HDL latency is 4 samples

Different DARadix Values for Each Stage

You can also specify different DARadix values for each filter in a cascade. You can only specify different cascade partitions on the command-line. When you specify partitions in the Generate HDL dialog box, all cascade stages use the same partitions. Inspect the results of hdlfilterdainfo to set DARadix values for each stage.

generatehdl(casc,'InputDataType',nt1, ...
'DALUTPartition',{[3 2],[2 2 1]},'DARadix',{2^3,2^7})
### Starting VHDL code generation process for filter: casfilt
### Cascade stage # 1
### Starting VHDL code generation process for filter: casfilt_stage1
### Generating: \\fs-21-ah\home$\bvenkata\Documents\MATLAB\Examples\hdlfilter-ex17169310\hdlsrc\casfilt_stage1.vhd
### Starting generation of casfilt_stage1 VHDL entity
### Starting generation of casfilt_stage1 VHDL architecture
### Clock rate is 5 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: casfilt_stage1
### Cascade stage # 2
### Starting VHDL code generation process for filter: casfilt_stage2
### Generating: \\fs-21-ah\home$\bvenkata\Documents\MATLAB\Examples\hdlfilter-ex17169310\hdlsrc\casfilt_stage2.vhd
### Starting generation of casfilt_stage2 VHDL entity
### Starting generation of casfilt_stage2 VHDL architecture
### Clock rate is 5 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: casfilt_stage2
### Generating: \\fs-21-ah\home$\bvenkata\Documents\MATLAB\Examples\hdlfilter-ex17169310\hdlsrc\casfilt.vhd
### Starting generation of casfilt VHDL entity
### Starting generation of casfilt VHDL architecture
### Successful completion of VHDL code generation process for filter: casfilt
### HDL latency is 4 samples

Specify different filter architectures for the different stages of a cascaded filter. You can specify a mix of serial, distributed arithmetic (DA), and parallel architectures depending upon your hardware constraints.

Create Cascaded Filter

Create a three-stage filter. Each stage is a different type.

h1 = dsp.FIRFilter('Numerator',[0.05 -.25 .88 0.9 .88 -.25 0.05]);
h2 = dsp.FIRFilter('Numerator',[-0.008 0.06 -0.44 0.44 -0.06 0.008], ...
    'Structure','Direct form antisymmetric');
h3 = dsp.FIRFilter('Numerator',[-0.008 0.06 0.44 0.44 0.06 -0.008], ...
    'Structure','Direct form symmetric');
casc = cascade(h1,h2,h3);

Specify Architecture for Each Stage

Specify a DA architecture for the first stage, a serial architecture for the second stage, and a fully parallel (default) architecture for the third stage.

To obtain DARadix values for the first architecture, use hdlfilterdainfo, then pick a value from dr.

nt = numerictype(1,12,10);
[dp,dr,lutsize,ff] = hdlfilterdainfo(casc.Stage1, ...
    'InputDataType',numerictype(1,12,10));
dr
dr = 6x1 cell array
    {'2^12'}
    {'2^6' }
    {'2^4' }
    {'2^3' }
    {'2^2' }
    {'2^1' }

Set the property values as cell arrays, where each cell applies to a stage. To disable a property for a particular stage, use default values (-1 for the partitions and 2 for DARadix).

generatehdl(casc,'InputDataType',nt, ...
    'SerialPartition',{-1,3,-1}, ...
    'DALUTPartition',{[4 3],-1,-1}, ...
    'DARadix',{2^6,2,2});
Warning: Structure fir has symmetric coefficients, consider converting to structure symmetricfir for reduced area.
Warning: Structure fir has symmetric coefficients, consider converting to structure symmetricfir for reduced area.
Warning: Structure fir has symmetric coefficients, consider converting to structure symmetricfir for reduced area.
### Starting VHDL code generation process for filter: casfilt
### Cascade stage # 1
### Starting VHDL code generation process for filter: casfilt_stage1
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex13094988/hdlsrc/casfilt_stage1.vhd
### Starting generation of casfilt_stage1 VHDL entity
### Starting generation of casfilt_stage1 VHDL architecture
### Clock rate is 2 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: casfilt_stage1
### Cascade stage # 2
### Starting VHDL code generation process for filter: casfilt_stage2
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex13094988/hdlsrc/casfilt_stage2.vhd
### Starting generation of casfilt_stage2 VHDL entity
### Starting generation of casfilt_stage2 VHDL architecture
### Clock rate is 3 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: casfilt_stage2
### Cascade stage # 3
### Starting VHDL code generation process for filter: casfilt_stage3
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex13094988/hdlsrc/casfilt_stage3.vhd
### Starting generation of casfilt_stage3 VHDL entity
### Starting generation of casfilt_stage3 VHDL architecture
### Successful completion of VHDL code generation process for filter: casfilt_stage3
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex13094988/hdlsrc/casfilt.vhd
### Starting generation of casfilt VHDL entity
### Starting generation of casfilt VHDL architecture
### Successful completion of VHDL code generation process for filter: casfilt
### HDL latency is 3 samples

You can specify input coefficients to test a filter with programmable coefficients.

Create a direct-form symmetric FIR filter with a fully parallel (default) architecture. Define the coefficients for the filter object in the vector b. The coder generates test bench code to test the coefficient interface using a second set of coefficients, c. The coder trims c to the effective length of the filter.

b = [-0.01 0.1 0.8 0.1 -0.01];
c = [-0.03 0.5 0.7 0.5 -0.03];
c = c(1:ceil(length(c)/2));
filt = dsp.FIRFilter('Numerator',b,'Structure','Direct form symmetric');
generatehdl(filt,'InputDataType',numerictype(1,16,15), ...
    'GenerateHDLTestbench','on', ...
    'CoefficientSource','ProcessorInterface','TestbenchCoeffStimulus',c)
### Starting VHDL code generation process for filter: firfilt
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex66247050/hdlsrc/firfilt.vhd
### Starting generation of firfilt VHDL entity
### Starting generation of firfilt VHDL architecture
### Successful completion of VHDL code generation process for filter: firfilt
### HDL latency is 2 samples
### Starting generation of VHDL Test Bench.
### Generating input stimulus
### Done generating input stimulus; length 3107 samples.
### Generating Test bench: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex66247050/hdlsrc/firfilt_tb.vhd
### Creating stimulus vectors ...
### Done generating VHDL Test Bench.

Create a filter specification. When you generate HDL code, specify a programmable interface for the coefficients.

Fs = 48e3;  
Fc = 10.8e3;
N = 5;
f_lp = fdesign.lowpass('n,f3db',N,Fc,Fs);
filtiir = design(f_lp,'butter','FilterStructure','df2sos','SystemObject',true);
filtiir.OptimizeUnityScaleValues = 0;
generatehdl(filtiir,'InputDataType',numerictype(1,16,15), ...
    'CoefficientSource','ProcessorInterface')
### Starting VHDL code generation process for filter: filtiir
### Generating: /tmp/Bdoc19b_1192687_40257/tp06f2f641/hdlfilter-ex92389569/hdlsrc/filtiir.vhd
### Starting generation of filtiir VHDL entity
### Starting generation of filtiir VHDL architecture
### Second-order section, # 1
### Second-order section, # 2
### First-order section, # 3
### Successful completion of VHDL code generation process for filter: filtiir
### HDL latency is 2 samples

The coder generates this VHDL entity for the filter object.

Explore various ways to specify clock ports for multirate filters.

Default Setting

Create a polyphase sample rate converter. By default, the coder generates a single input clock (clk), an input clock enable (clk_enable), and a clock enable output signal named ce_out. The ce_out signal indicates when an output sample is ready. The ce_in output signal indicates when an input sample was accepted. You can use this signal to control the upstream data flow.

firrc = dsp.FIRRateConverter('InterpolationFactor',5,'DecimationFactor',3);
generatehdl(firrc,'InputDataType',numerictype(1,16,15))
### Starting VHDL code generation process for filter: firrc
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex09049114/hdlsrc/firrc.vhd
### Starting generation of firrc VHDL entity
### Starting generation of firrc VHDL architecture
### Successful completion of VHDL code generation process for filter: firrc
### HDL latency is 2 samples

The generated entity has the following signals:

Custom Clock Names

You can provide custom names for the input clock enable and the output clock enable signals. You cannot rename the ce_in signal.

firrc = dsp.FIRRateConverter('InterpolationFactor',5,'DecimationFactor',3)
firrc = 
  dsp.FIRRateConverter with properties:

    InterpolationFactor: 5
       DecimationFactor: 3
              Numerator: [1x71 double]

  Show all properties

generatehdl(firrc,'InputDataType',numerictype(1,16,15),...
            'ClockEnableInputPort','clk_en1', ...
            'ClockEnableOutputPort','clk_en2')
### Starting VHDL code generation process for filter: firrc
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex09049114/hdlsrc/firrc.vhd
### Starting generation of firrc VHDL entity
### Starting generation of firrc VHDL architecture
### Successful completion of VHDL code generation process for filter: firrc
### HDL latency is 2 samples

The generated entity has the following signals:

Multiple Clock Inputs

To generate multiple clock input signals for a supported multirate filter, set the ClockInputs property to 'Multiple'. In this case, the coder does not generate any output clock enable ports.

decim = dsp.CICDecimator(7,1,4);
generatehdl(decim,'InputDataType',numerictype(1,16,15), ...
    'ClockInputs','Multiple')
### Starting VHDL code generation process for filter: cicDecOrIntFilt
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex09049114/hdlsrc/cicDecOrIntFilt.vhd
### Starting generation of cicDecOrIntFilt VHDL entity
### Starting generation of cicDecOrIntFilt VHDL architecture
### Section # 1 : Integrator
### Section # 2 : Integrator
### Section # 3 : Integrator
### Section # 4 : Integrator
### Section # 5 : Comb
### Section # 6 : Comb
### Section # 7 : Comb
### Section # 8 : Comb
### Successful completion of VHDL code generation process for filter: cicDecOrIntFilt
### HDL latency is 7 samples

The generated entity has the following signals:

Create a filter object. Then call generatehdl , and specify a synthesis tool.

lpf = fdesign.lowpass('fp,fst,ap,ast',0.45,0.55,1,60);
firfilt = design(lpf,'equiripple','FilterStructure','dfsymfir', ...
    'SystemObject',true);
generatehdl(firfilt,'InputDataType',numerictype(1,14,13), ...
    'HDLSynthTool','Quartus');
### Starting VHDL code generation process for filter: firfilt
### Generating: /tmp/Bdoc19b_1192687_40257/tp06f2f641/hdlfilter-ex92219095/hdlsrc/firfilt.vhd
### Starting generation of firfilt VHDL entity
### Starting generation of firfilt VHDL architecture
### Successful completion of VHDL code generation process for filter: firfilt
### HDL latency is 2 samples

The coder generates a script file named firfilt_quartus.tcl, using the default script properties for the Altera® Quartus II synthesis tool.

type hdlsrc/firfilt_quartus.tcl
load_package flow
set top_level firfilt
set src_dir "./hdlsrc"
set prj_dir "q2dir"
file mkdir ../$prj_dir
cd ../$prj_dir
project_new $top_level -revision $top_level -overwrite
set_global_assignment -name FAMILY "Stratix II"
set_global_assignment -name DEVICE EP2S60F484C3
set_global_assignment -name TOP_LEVEL_ENTITY $top_level
set_global_assignment -name vhdl_FILE "../$src_dir/firfilt.vhd"
execute_flow -compile
project_close

You can set the script automation properties to dummy values to illustrate how the coder constructs the synthesis script from the properties.

Design a filter and generate HDL. Specify a synthesis tool and custom text to include in the synthesis script.

lpf = fdesign.lowpass('fp,fst,ap,ast',0.45,0.55,1,60);
firfilt = design(lpf,'equiripple','FilterStructure','dfsymfir', ...
    'Systemobject',true);
generatehdl(firfilt,'InputDataType',numerictype(1,14,13), ...
    'HDLSynthTool','ISE', ...
    'HDLSynthInit','init line 1 : module name is %s\ninit line 2\n', ...
    'HDLSynthCmd','command : HDL filename is %s\n', ...
    'HDLSynthTerm','term line 1\nterm line 2\n');
### Starting VHDL code generation process for filter: firfilt
### Generating: /tmp/Bdoc19b_1192687_39409/tp25fa77a2/hdlfilter-ex64737676/hdlsrc/firfilt.vhd
### Starting generation of firfilt VHDL entity
### Starting generation of firfilt VHDL architecture
### Successful completion of VHDL code generation process for filter: firfilt
### HDL latency is 2 samples

The coder generates a script file named firfilt_ise.tcl. Note the locations of the custom text you specified. You can use this feature to add synthesis instructions to the generated script.

type hdlsrc/firfilt_ise.tcl
init line 1 : module name is firfilt
init line 2
command : HDL filename is firfilt.vhd
term line 1
term line 2

Input Arguments

collapse all

Filter from which to generate HDL code, specified as a filter System object. To create a filter System object, use the design function or see the reference page of the object. You can use the following System objects from DSP System Toolbox™:

Input data type, specified as a numerictype object. This argument applies only when the input filter is a System object. Call numerictype(s,w,f), where s is 1 for signed and 0 for unsigned, w is the word length in bits, and f is the number of fractional bits.

Fractional delay data type, specified as a numerictype object. This argument applies only when the input filter is a dsp.VariableFractionalDelay System object. Call numerictype(s,w,f), where s is 1 for signed and 0 for unsigned, w is the word length in bits, and f is the number of fractional bits.

Filter from which to generate HDL code, specified as a dfilt object. You can create this object by using the design function. For an overview of supported filter features, see Filter Configuration Options.

Alternatives

You can use the fdhdltool function to generate HDL code instead. Specify the input and fractional delay data types as arguments, and then set additional properties in the Generate HDL dialog box.

Introduced before R2006a