HDL Port and Identifier Properties

Customize ports, identifiers, and comments

With the HDL port and identifier properties, you can customize ports, identifiers, and comments in the generated code.

Specify these properties as comma-separated pairs of Name,Value arguments to the generatehdl function. Name is the property name and Value is the corresponding value. Name must appear inside single quotes (' '). You can specify several name and value pair arguments in any order as Name1,Value1,...,NameN,ValueN.

For example:

fir = dsp.FIRFilter('Structure','Direct form antisymmetric');
generatehdl(fir,'InputDataType',numerictype(1,16,15),'ClockInputPort','clk_input');

Clocks, Inputs, and Outputs

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Name of clock enable input port, specified as 'clk_enable', a character vector, or a string scalar.

If you specify a value that is a reserved word in the target language, the coder adds the postfix _rsvd to this value. You can update the postfix value by using the ReservedWordPostfix property. For more details, see Resolving HDL Reserved Word Conflicts.

Name of clock enable output port, specified as 'ce_out', a character vector, or a string scalar. This property applies only to Multirate Filters that use a single input clock (default behavior of ClockInputs). For an example, see Clock Ports for Multirate Filters. For more details, see Code Generation Options for Multirate Filters.

If you specify a value that is a reserved word in the target language, the coder adds the postfix _rsvd to this value. You can update the postfix value by using the ReservedWordPostfix property. For more details, see Resolving HDL Reserved Word Conflicts.

Name of clock input port, specified as 'clk', a character vector, or a string scalar.

If you specify a value that is a reserved word in the target language, the coder adds the postfix _rsvd to this value. You can update the postfix value by using the ReservedWordPostfix property. For more details, see Resolving HDL Reserved Word Conflicts.

Name of filter input port, specified as 'filter_in', a character vector, or a string scalar.

If you specify a value that is a reserved word in the target language, the coder adds the postfix _rsvd to this value. You can update the postfix value by using the ReservedWordPostfix property. For more details, see Resolving HDL Reserved Word Conflicts.

Data type of filter input port, specified as one of the following:

  • 'std_logic_vector' or 'signed/unsigned' (when the target language is VHDL)

  • 'wire' (when the target language is Verilog)

Name of filter output port, specified as 'filter_out', a character vector, or a string scalar.

If you specify a value that is a reserved word in the target language, the coder adds the postfix _rsvd to this value. You can update the postfix value by using the ReservedWordPostfix property. For more details, see Resolving HDL Reserved Word Conflicts.

Data type of filter output port in generated HDL code, specified as one of the following:

  • 'Same as input data type', 'std_logic_vector', or 'signed/unsigned' (when the target language is VHDL)

  • 'wire' (when the target language is Verilog)

Resets

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Name of filter reset port, specified as 'reset', a character vector, or a string scalar. Use the ResetAssertedLevel property to control the behaviour of this port.

If you specify a value that is a reserved word in the target language, the coder adds the postfix _rsvd to this value. You can update the postfix value by using the ReservedWordPostfix property. For more details, see Resolving HDL Reserved Word Conflicts.

Suppress the generation of resets from the shift registers, specified as 'none' or 'ShiftRegister'. To omit reset signals from shift registers, set this property to 'ShiftRegister'. Disabling reset signals from shift registers can result in a more efficient FPGA implementation. For more details, see Suppressing Generation of Reset Logic.

Asserted (active) level of reset input signal, specified as one of the following:

  • 'active-high' — To reset registers in the filter design, the reset input signal must be driven high (1).

    For example, this code checks whether reset is active high before populating the delay_pipeline register.

    Delay_Pipeline_Process : PROCESS (clk, reset)
    BEGIN
      IF reset = '1' THEN
        delay_pipeline(0 TO 50) <= (OTHERS => (OTHERS => '0'));

  • 'active-low' — To reset registers in the filter design, the reset input signal must be driven low (0).

    For example, this code checks whether reset is active low before populating the delay_pipeline register.

    Delay_Pipeline_Process : PROCESS (clk, reset)
    BEGIN
      IF reset = '0' THEN
        delay_pipeline(0 TO 50) <= (OTHERS => (OTHERS => '0'));

Reset style for registers, specified as one of the following:

  • 'async' — The coder uses asynchronous resets. The HDL process block does not check for an active clock before performing a reset. For example:

    delay_pipeline_process : PROCESS (clk, reset)
    BEGIN
      IF Reset_Port = '1' THEN
        delay_pipeline (0 To 50) <= (OTHERS =>(OTHERS => '0'));
      ELSIF Clock_Port'event AND Clock_Port = '1' THEN
        IF ClockEnable_Port = '1' THEN
          delay_pipeline(0) <= signed(Fin_Port);
          delay_pipeline(1 TO 50) <= delay_pipeline(0 TO 49);
        END IF;
      END IF;
    END PROCESS delay_pipeline_process;

  • 'sync' — The coder uses a synchronous reset style. In this case, the HDL process block checks for the rising edge of the clock before performing a reset. For example:

    delay_pipeline_process : PROCESS (clk, reset)
    BEGIN
      IF rising_edge(Clock_Port) THEN
        IF Reset_Port = '0' THEN
         delay_pipeline(0 To 50) <= (OTHERS =>(OTHERS => '0'));
        ELSIF ClockEnable_Port = '1' THEN
         delay_pipeline(0) <= signed(Fin_Port);
         delay_pipeline(1 TO 50) <= delay_pipeline(0 TO 49);
        END IF;
      END IF;
    END PROCESS delay_pipeline_process;
    

Identifiers and Comments

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Postfix to the block section labels, specified as '_gen', a character vector, or a string scalar. This property applies only when the target language is VHDL. The coder appends this postfix to the block section labels of VHDL GENERATE statements.

Postfix to the instance section labels, specified as '_gen', a character vector, or a string scalar. This property applies only when the target language is VHDL. The coder appends this postfix to the instance section labels of VHDL GENERATE statements.

Postfix to output assignment block labels, specified as 'outputgen', a character vector, or a string scalar. This property applies only when the target language is VHDL. The coder appends this postfix to the output assignment block labels of VHDL GENERATE statements.

Postfix to HDL clock process names, specified as '_process', a character vector, or a string scalar. The coder uses HDL process blocks to modify the content of the registers in the filter. The block label is derived from the register name and this postfix. For example, in the following block declaration, the coder derives the process label from the register name delay_pipeline and the default postfix '_process'.

delay_pipeline_process : PROCESS (clk, reset)
BEGIN

Prefix for filter coefficient names, specified as 'coeff', a character vector, or a string scalar. The coder derives the coefficient names by appending filter-specific characteristics to this prefix.

Filter TypeCoefficient Name
FIRThe coder appends the coefficient number to CoeffPrefix, starting with 1. For example, the default for the first coefficient is coeff1.
IIR

The coder appends the following characters to CoeffPrefix:

  1. underscore (_)

  2. a or b coefficient name (for example, _a2, _b1, or _b2)

  3. _sectionN, where N is the section number.

For example, the default for the first numerator coefficient of the third section is coeff_b1_section3.

For example:

firfilt = design(fdesign.lowpass,'equiripple', ...
    'FilterStructure','dfsymfir','SystemObject',true);
generatehdl(firfilt,'InputDataType',numerictype(1,16,15), ...
    'CoefficientSource','Internal','CoeffPrefix','mycoeff');

The coder replaces the default coefficient name prefix with the custom value:

ARCHITECTURE rtl OF firfilt IS
  -- Local Functions
  -- Type Definitions
  TYPE delay_pipeline_type IS ARRAY (NATURAL range <>) OF signed(15 DOWNTO 0); -- sfix16_En15
  -- Constants
  CONSTANT mycoeff1   : signed(15 DOWNTO 0) := to_signed(-159, 16); -- sfix16_En16
  CONSTANT mycoeff2   : signed(15 DOWNTO 0) := to_signed(-137, 16); -- sfix16_En16
  CONSTANT mycoeff3   : signed(15 DOWNTO 0) := to_signed(444, 16); -- sfix16_En16
  CONSTANT mycoeff4   : signed(15 DOWNTO 0) := to_signed(1097, 16); -- sfix16_En16
  ...

Dependencies

This property applies only when you set CoefficientSource to 'Internal'.

Postfix to imaginary part of complex signal names, specified as '_im', a character vector, or a string scalar. See Using Complex Data and Coefficients.

Postfix to real part of complex signal names, specified as '_re', a character vector, or a string scalar. See Using Complex Data and Coefficients.

Postfix to duplicate entity or module names, specified as '_block', a character vector, or a string scalar. The coder appends this postfix to resolve duplicate VHDL entity or Verilog module names. For example, if the coder detects two entities with the name MyFilt, the coder names the first entity MyFilt and the second instance MyFilt_block.

Prefix for component instance name, specified as 'u_', a character vector, or string scalar.

Postfix to VHDL package file name, specified as '_pkg', a character vector, or a string scalar. The coder derives the package name by appending this postfix to the filter name. This option applies only if a package file is required for the design.

Postfix to reserved words, specified as '_rsvd', a character vector, or a string scalar. This property applies to name, postfix, or label values specified as a character vector or a string scalar in Name,Value pair arguments to generatehdl. If a specified value is a reserved word in the target language, the coder appends this postfix to the value. For example, if you call generatehdl with the argument pair 'Name','mod', the coder forms the name mod_rsvd in the generated filter code. See Reserved Word Tables.

Split VHDL entity and architecture code, specified as 'off' or 'on'. When this property is set to 'on', the coder generates the VHDL entity and architecture code of the filter in two separate files. The coder derives the file names from the filter name by appending the postfixes _entity and _arch to the base file name. To specify custom postfix values, set the SplitEntityFilePostfix and SplitArchFilePostfix properties.

Postfix to VHDL architecture file name, specified as '_arch', a character vector, or a string scalar.

Dependencies

This property applies only when you set SplitEntityArch to 'on'.

Postfix to VHDL entity file name, specified as '_entity', a character vector, or a string scalar.

Dependencies

This property applies only when you set SplitEntityArch to 'on'.

Add user comments to generated HDL code, specified as a character vector or string vector. The user comments appear in the header comment block at the top of the generated files, preceded by leading comment characters specific to the target language. When you include new lines or line feeds in the user comments, the coder emits single-line comments for each new line. For example:

firfilt = dsp.FIRFilter;
generatehdl(firfilt,'InputDataType',numerictype(1,16,15), ...
    'UserComment','This is a comment line.\nThis is a second line.')
The resulting header comment block for the filter firfilt is as follows:
-- -------------------------------------------------------------
--
-- Module: firfilt
-- Generated by MATLAB(R) 9.1 and the Filter Design HDL Coder 3.1.
-- Generated on: 2016-11-08 15:28:25
-- This is a comment line.
-- This is a second line.
--
-- -------------------------------------------------------------

-- -------------------------------------------------------------
-- HDL Code Generation Options:
--
-- TargetLanguage: VHDL
-- Name: firfilt
-- InputDataType: numerictype(1,16,15)
-- UserComment:  User data, length 47
-- GenerateHDLTestBench: off

-- -------------------------------------------------------------
-- HDL Implementation    : Fully parallel
-- Folding Factor        : 1
-- -------------------------------------------------------------
-- Filter Settings:
--
-- Discrete-Time FIR Filter (real)
-- -------------------------------
-- Filter Structure  : Direct-Form FIR
-- Filter Length     : 2
-- Stable            : Yes
-- Linear Phase      : Yes (Type 2)
-- Arithmetic        : fixed
-- Numerator         : s16,15 -> [-1 1)
-- -------------------------------------------------------------

Prefix for VHDL vector signal names, specified as 'vector_of_', a character vector, or a string scalar.

Tips

If you use the function fdhdltool to generate HDL code, you can set the corresponding properties in the Generate HDL dialog box.

PropertyLocation in Dialog Box

Input data type

Output data type

Clock enable output port

Input port

Output port

Global Settings tab > Ports tab
Additional port and identifier properties

Top section of Global Settings tab, and Global Settings tab > General tab

Check out the main Global Settings tab, and the Ports and General tabs of the Global Settings tab.

Introduced before R2006a