Customize SerDes Systems

Modify MATLAB scripts or Simulink models exported from SerDes Designer app

Use the SerDes Designer app to develop a SerDes system based on statistical BER analysis. Export the SerDes system to a Simulink^® model or MATLAB^® script.

Modify the Simulink model to customize the control parameters in the building blocks. You can add or modify your own parameters to develop your own SerDes system. Perform statistical analysis and time-domain simulation to validate your system.

You can also modify the MATLAB script to perform further statistical analysis and time-domain simulation and automate the analysis process.

Apps

SerDes Designer

Design and analyze SerDes systems for export to Simulink, MATLAB and IBIS-AMI

Topics

Customize SerDes System in MATLAB
Modify system objects in the MATLAB script to customize the SerDes systems.
Access Simulation Results in Simulink
Learn how to access simulation results from model workspace.

Featured Examples

Customizing SerDes Toolbox Datapath Control Signals

Customize the control signals in a SerDes system datapath by adding new custom AMI parameters and using MATLAB® function blocks. This allows you to customize existing control parameters without modifying the built-in blocks in the SerDes Toolbox™ library.

Open Script

Customizing Datapath Building Blocks

Customize a PassThrough block in Simulink® to use a MATLAB® function block or other Simulink library blocks. You will see how the implementation of a receiver gain or attenuation stage is controlled by an IBIS-AMI parameter, and this example provides a guide to modify PassThrough blocks to implement custom functions for a SerDes system.

Open Live Script

Implement Custom CTLE in SerDes Toolbox PassThrough Block

Customize a PassThrough Block in Simulink® to implement a CTLE System object™ with user defined AMI parameters. You can use this example as a guide for modifying PassThrough blocks that leverage system objects. For more information on the purpose of the PassThrough block and an example of using other Simulink library blocks within them, see Customizing Datapath Building Blocks.

Open Live Script

Step Response Based CTLE

Create a custom step response-based CTLE block in Simulink® to model wired communication links of your own specifications. The custom CTLE block exhibits equivalent behavior as the default pole/zero based CTLE block from the SerDes Toolbox™. This example also illustrates:

Open Live Script

Generate HDL for Dual-Summing-Node DFE

Design a bit-accurate decision feedback equalizer (DFE) adaptation engine for an architecturally representative 100-Gb/s dual-summing-node-DFE PAM4 SerDes receiver model using blocks from the SerDes Toolbox™. This bit-accurate DFE adaptation engine generates synthesizable RTL code that is suitable for implementation in an ASIC or an FPGA. The implementation-representative datapath in the DFE model enables the adaptation engine to reflect key design aspects: PAM4 threshold recovery, DFE tap weight adjustment, and clock phase sensitivity.

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Verify Standalone CTLE in Architectural, Behavioral, and Circuit Domains

Simulates a continuous-time linear equalizer (CTLE) in several design domains, while keeping the underlying models in synchronization through tool automation. The Simulink® architectural model acts as a high-level specification of the desired analog circuit behavior. Using HDL Verifier™, export the standalone CTLE model into a SystemVerilog behavioral model. The exported model enables early digital control development for analog calibration before you design the analog circuit. A circuit implementation of the CTLE is characterized (offline) using analog simulations. The characterization results are then fed back into the architectural model. This converts the specification-based Simulink model into a circuit-representative model. Both specification and circuit-representative models of the CTLE are provided as part of this example. Use HDL Verifier to regenerate the SystemVerilog behavioral model. This model can be used for mixed-signal validation; turning the specification-based SystemVerilog model into a circuit-representative SystemVerilog model. This automation keeps the architectural, behavioral, and circuit models in synchronicity.

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Verify SerDes Toolbox CTLE in Architectural, Behavioral, and Circuit Domains

Demonstrates a workflow to simulate a continuous-time linear equalizer (CTLE) in several design domains, while keeping the underlying models in synchronization through tool automation.

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Verify Multi-Path ADC in Architectural, Behavioral, and Circuit Domains

Use a time-interleaved analog to digital converter (ADC) from Mixed-Signal Blockset™ to develop an offset and gain calibration engine for mismatched interleaved ADC paths. For an architectural representation of time-interleaved ADC for IBIS-AMI export, see the ADC IBIS-AMI Model based on COM and Architectural 112G PAM4 ADC-Based SerDes Model examples.

Open Live Script