how could i generate an axi-stream or axi4-lite dma master by hdl coder?

Hi, i found the current demo using only axi-stream slave interface in sobel image processing system. however, it might require a master to access DDR on zc-702 for other application in the future. but i don't know how am i going to create a simulink design with this kind of functionality, or does hdl coder support this code generation yet?

Thanks

Owen

Answer 1

[Wang Chen]

Hi Owen,

HDL Coder doesn't support AXI4-Lite Master mode yet. The current AXI4-Lite support is for slave mode only. You can use ARM processor to control the DMA controller, or use Xilinx AXI Master Lite IP if you want to control the DAM controller from your IP core directly. We are planning to support the AXI4-Lite master mode in the future releases.

The Sobel image processing demo is using both the AXI4-Stream Video master and slave interface. The Input video streaming is the slave interface, the output video streaming is the master interface.

Please let me know if you have any questions.

Thanks, Wang

[sankula sivasankar]

how could i read image from VDMA in zynq using mat lab code for conversion with HDL coder

[pd7]

Unable to see AXI Video stream in/out on HDL Advisor for the Sobel filter reference design. I have updated the hardware support packages. My target is either Zybo or Zedboard. I also tried choosing Generic. I have followed all the steps in the http://in.mathworks.com/help/hdlcoder/examples/using-ip-core-generation-workflow-sobel-edge-detection.html