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Connect AXI4 Master to multiple slaves
Hi John, addAXI4MasterInterface method only support connecting to one slave device currently. If you are creating AMD Vivado ...
25 jours il y a | 0
HDL Coder Error when converting AXI4 interface with different data rates
Hi John, From the error message, it looks like you are using the "AXI4 Master" interface. HDL Coder currently requires the D...
environ 2 mois il y a | 0
| A accepté
Definition of "Frame" for Recurrent models
Hi Tommaso, To clarify, when running an LSTM network, the term "Frame" in the estimatePerformance report refers to an element ...
11 mois il y a | 0
Issue with LSTM OutputMode='last' in MATLAB Deep Learning HDL Toolbox
Hi Tommaso, The "OutputMode" property = "last" is not supported in Deep Learning HDL Toolbox yet. https://www.mathworks.com/...
11 mois il y a | 1
| A accepté
what kind of basic FPGA system is needed for deep learning IP core generation?
Hi KH, On top of Kanishk's answer, you can also refer to following example: https://www.mathworks.com/help/deep-learning-hdl/...
environ un an il y a | 0
how to download the third party support package file "xilinx linux binaries"
Hi KH, In "HDL Coder Support Package for Xilinx FPGA and SoC Devices." hardware setup GUI, there is a choice for manually down...
environ un an il y a | 1
the compilation failed due to timing violation
Hi Madhusudan, To clarify, it looks like you are trying to run the HDL Coder generated HDL code using 40MHz clock, and the NI ...
plus d'un an il y a | 0
| A accepté
[Error in dnnfpga.apis.Workflow/compileNetwork] - Enable the Resize2D
Hi Ngo, The resize2DLayer inside of the Yolo v3 network is not yet supported by DL HDL Toolbox on Intel boards like Arria 10 S...
environ 2 ans il y a | 0
| A accepté
How to add TCL script to HDL Coder IP Core generation
Hi Alex, To clarify, "add additional sources" option (in HDL Workflow Advisor "Generate RTL code and IP core" step) is intende...
plus de 2 ans il y a | 0
| A accepté
Why do I get error messages while installing "HDL Coder Package for RFSoC" in MATLAB R2021b ?
Hi Jyotirmaya, I just tried on my R2021b, that I can successfully install "HDL Coder Support Package for Xilinx RFSoC Devices"...
plus de 2 ans il y a | 0
error compiling ResNet50 Deep Learning HDL Toolbox Support Package
Hi Ruben, For Resnet50 network, have you tried to download the Deep Learning Toolbox Model for ResNet-50 Network support pacak...
plus de 2 ans il y a | 0
Error configuring Nertwork Interface Card (NIC) Deep Learning HDL Toolbox Support Package For Intel FPGA And SoC Devices
Hi Ruben, Alternatively, you could skip this step (check the check box "Skip this step if your network card is already configu...
plus de 2 ans il y a | 0
nnet.keras.layer.FlattenCStyleLayer is not supported
Hi Ruben, Is it possible for you to upgrade to R2022a or higher version of MATLAB? This issue is fixed in R2022a, please see ...
plus de 2 ans il y a | 0
Callback Functions for Custom Reference Design doesn't work
Hi borzack, As you commented, this is likely caused by that MATLAB cannot find my_board.my_ref_design.callback_CustomizeReferen...
plus de 3 ans il y a | 0
| A accepté
Error selecting target in R2020a and Vivado 2020
Hi Miquel, For Spartan-6 FPGA device, Xilinx requires Xilinx ISE as synthesis tool. You cannot use Xilinx Vivado for Spartan-6...
presque 4 ans il y a | 0
| A accepté
Running ZYNQ model on different host computer rather than computer on which bit file is generated
Hi Muhammad, This error looks like related to the Embedded Coder build tool chain setup. HDL Workflow Advisor only generate t...
presque 4 ans il y a | 0
using the HDL workflow advisor for a single registration target which need to include two or more matlab users IP CORES
Hi Raz, It is true that HDL Workflow Advisor currently generates just one User IP core at a time. We are working on removing t...
environ 4 ans il y a | 0
How to access AXI-registers of IP-blocks that are already part of custom reference design, not generated with HDLCoder?
Hi Jiarno, HDL Verifier has a MATLAB as AXI Master feature, which you can from MATLAB to control different IPs in your FPGA de...
plus de 4 ans il y a | 0
How do vectorized ports in hdl coder work?
Hi Jay, The expected behaivor is to get [1 2] value for the vector port. This should already be fixed in newer version of t...
plus de 4 ans il y a | 0
Reading Data from PMOD ADC through I2C
Hi Jay, Yes, I2C readback need some extra logic. The HDL Coder example model you mentioned only do I2C write. As Walter menti...
plus de 4 ans il y a | 0
How do I add/register multiple axi interfaces in a zynq reference design?
Hi Hong, HDL Coder generated IP core can only have one AXI4 slave interface. In latest version of MATLAB, HDL Coder will error...
plus de 4 ans il y a | 0
Bad Timing Delays after insterting IP Core generated from Simulink
Hi Alex, It looks like your model does potentially has a long critical path, as I don't see any pipeline delays on the data pa...
environ 5 ans il y a | 0
HDL Coder - Can it only Generate a project with Vivado 2107.2, not Vivado 2017.4.1
Hi Mike, R2018a version of HDL Coder supports Vivado 2017.2, so please use this version of Vivado. Please see following doc...
plus de 7 ans il y a | 0
| A accepté
Signal measurement error when using "download"-option in HDL Workflow Advisor
Hi Frederik, When you are using the "Download" programming method, the FPGA bitstream is programmed during the Linux boot up...
presque 8 ans il y a | 0
| A accepté
hdl coder led blinking example
Hi Bence, are you using Vivado 2017.4? We noticed that Vivado 2017.4 starts to error out on unconnected AXI Master ports in the ...
presque 8 ans il y a | 0
| A accepté
Is it possible to create a custom board for the HDL Coder with the zynq z7100
Hi Patrick, Yes, when using IP core generation workflow in HDL Coder, you can create custom board support for a board with Zynq...
environ 8 ans il y a | 0
| A accepté
How to set up Altera Cyclone V SoC Development Kit for Embedded Coder Support Package?
Hi Netanel, Do you mean the serial connection (USB UART) is timing out? Please set the jumper setting the same as the pic...
environ 9 ans il y a | 0
Unable to see AXI Video stream in/out on HDL Advisor for the Sobel filter reference design.
Hi, are you using Xilinx ISE as synthesis tool? In R2016a or earlier version, the "AXI4-Stream Video" interface is only support ...
plus de 9 ans il y a | 1
| A accepté
How to solve the problem of the file "system_top_wrapper.bit is not found"?
Hi Yahia, This is a bug in HDL Workflow Advisor. Thanks for reporting this! This bug is already fixed in MATLAB version R2...
plus de 9 ans il y a | 1
AD9467 HDL Coder adding Custom Reference Design - create_bc_cell issue
The Vivado error message is complaining that it cannot find an IP (analog.com:user:axi_ad9467:1.0) when HDL Workflow Advisor is ...
presque 10 ans il y a | 0
