Using HDL Coder IP core in Xilinx Vivado instead of EDK

I need to use an IP core generated with HDL Coder in Xilinx Vivado 2014.2. The core generated by the coder is intended to be used in Xilinx EDK. The IP core converter implemented in Vivado 2014.2 has troubles to identify the AXI interfaces in my core correctly, so I would have to set the AXI parameters manually, which is a very time consuming task, especially if performed more than once. Will you support direct generation of IP cores for Vivado in the future?

Answer 1

[Wang Chen]

Hi Stefan,

Yes, the IP core generation feature for Xilinx Vivado will be supported in MATLAB R2014b release. You can already try out this feature in R2014b pre-release.

Thanks, Wang

[Stefan Schwarzer]

Thank you Wang, I installed R2014b prerelease and found the options for Vivado. Vivado implementation still seems to be pretty buggy: I get a synthesis error if I chose "Generic ASIC/FPGA implementation" (although the synthesis report looks good) and I get an error during HDL generation if i chose "IP core generation" and setup some AXI interfaces. I tried this out with the mlhdl_counter example, so nothing special.