How to add a custom parameter in the generated module with HDL Coder,simulink?

Hi,

I want to design an uart_tx module, which has two parameters clk_frequency and Baud_rate.

In verilog, the correct code is as below:

module uart_tx

#(

parameter CLK_FRE = 50, //clock frequency(Mhz)

parameter BAUD_RATE = 115200 //serial baud rate

)

So, which block can generate it? Thanks.

Answer 1

[Kiran Kintali]

How are generics supported in HDL Coder?

https://www.mathworks.com/support/search.html/answers/382489-how-are-generics-supported-in-hdl-coder.html