Error using () Data type mismatch at signal 'c_out'.This port expects a Logic data type of size 1

This is my full adder code

module fulladder ( input [3:0] a,

input [3:0] b,

input c_in,

output c_out,

output [3:0] sum);

assign {c_out, sum} = a + b + c_in;

endmodule

Im trying to run cosimWizard from matlab.

In output port details pane, i selected Double data type for c_out, and fixedpoint signed datatype for sum.

but im getting the below error

Error using ()

Data type mismatch at signal 'c_out'.This

port expects a Logic data type of size 1

what should i assign output datatypes for c_out and sum?

Answer 1

[Marc Erickson]

The module port declarations are (implicitly) declaring c_out and sum as net types of wire and data type of logic (1 bit and 4 bits respectively). The cosimulation interface will expect Simulink or MATLAB data types that match the bit widths in the Verilog.

I do not understand what the module implementation is trying to do, but you should reexamine that.

To use 'double' in MATLAB/Simulink: in Verilog, use a 64bit logic type and the $bitstoreal / $realtobits system functions.