difference in column based and element based decimated output of a down sampler

I am trying to down sample a 4 MHz signal . when i used the downsampler with input processing option Element based it outputs the same number of signals as we have without decimation.But wihen do i used the downsampler with input processing option coulmn based the number of signals are not same as input. Also when do i implement it on FPGA the number of signls are also impacted for both approaches. How could we resolve this issue. so that it outputs same number of signals in same pattern both in simulation and FPGA attached is the snap for different outputs

Answer 1

[Bharath Venkataraman]

Muhammad, I assume that you are doing this as a multirate system in the FPGA. To mimic that behavior, send in scalar input to the Downsample block and set the Rate Option to allow Multirate processing. The output will be scalar at the decimated/slower rate which should match your FPGA.