is it possible to prevent the compiler from using variables in generated VHDL code?

Hi,

is it possible to prevent the compiler from using the datatype "variable" in generated VHDL code? As it is an essential rule of my coding rule checker, i have to fix this issue.

In my case, the variables are generated inside of the FSM processes. (created with Stateflow)

(I know there is the option in the settings to minimize the use of variables but i doesnt change anything)

Thank you!

[Tom Richter]

Hi Eldin,

I assume this cannot be changed. Please provide a small model and reasons why variables are not allowed in your code to our Technical Support Team as described here. Is it possible to provide a justification to your coding rule checker so that it accepts variables in certain cases? What checker are you using.

Thanks,

Tom