fixing clock frequency and sample time of control system model using hdl coder

I have built a fixed point PID controller in simulink and could generate the code using hdl coder for programming FPGA. The generated verilog code has additional inputs such as clock, clock enable. During simulation, I fixed the sample time of the discrete models to .01 seconds. I am unable to understand the difference between the input clock and the sample time. Could you please clarify? (btw My FPGA recieves external clock of 50MHz)

Answer 1

[Kiran Kintali]

See the attached document on the concept of sample time in the model and its relation to clock in the generated code using HDL Coder.

Please share your sample model and target specifications for additional inputs.

https://www.mathworks.com/help/hdlcoder/examples.html?category=hdl-code-generation-from-simulink&exampleproduct=all&newonly=&s_tid=CRUX_lftnav

You may also find these videos interesting on clock rate pipelining

https://www.mathworks.com/support/search.html/videos/hdl-coder-clock-rate-pipelining-part-1-introduction-120117.html?fq%5B%5D=asset_type_name:video&fq%5B%5D=category:hdlcoder/index&page=1

https://www.mathworks.com/support/search.html/videos/hdl-coder-clock-rate-pipelining-part-2-optimization-120113.html?fq%5B%5D=asset_type_name:video&fq%5B%5D=category:hdlcoder/index&page=1