How to generate simulink model from multiple verilog codes?

I am trying to generate simulink model from almost 175 verilog files. Using importhdl it always shows some error whether i try using folder, subfolder, path or filenames. Is there any way to fix it?

Answer 1

[Kiran Kintali]

importhdl - Import Verilog code and generate Simulink model - MATLAB (mathworks.com)

Please note HDL Coder only supports a subset of synthesizable HDL suitable for a Simulink representation in this import process. You may be running into obvious limitations in the workflow. Not all Verilog/VHDL is importable to Simulink.

Added some intro slides on the importhdl command.

Can you share some more details? It is unclear the issues you are facing. Do not hesitate to reach out to tech support [e-mail]

[Jaykishan Solanki]

I wrote MATLAB scripts and then converted it to verilog, now I want to generate a simulink model to understand the flow of verilog code. But whenever I try this using importhdl it shows some error like the following:

Error using privimporthdl

Importhdl failed

Error in importhdl (line 78)

privimporthdl (hdlInSrc, varargin{:}) - Show complete stack trace

Displaying stack trace:

Error using privimporthdl

• In privimporthdl
• In importhdl (line 78)