Is it possible to integrate the HDL CODE generated by simulink into an existing user-defined vivado project?
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hello,everyone!Is it possible to integrate the HDL CODE generated by simulink into an existing user-defined vivado project? If possible, what do I need to pay attention to in the user-designed vivado project。
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Kiran Kintali
le 31 Déc 2024
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Generating an IP core wrapper for the HDL Coder generated code is the best way to integrate your algorithm into an existing vivado project. You can find the details below. However please note that you can go beyond just IP core and build an entire custom reference design for your board and work within MATLAB enviroment programming and interacting with the board.
HDL IP Core Generation
Deploy generated IP core on a target hardware platform
Generate a reusable HDL IP core to design a system that you can deploy on hardware or a combination of hardware and software. Deploy your MATLAB® or Simulink® design:
- As hardware and software on system-on-chip (SoC) platforms, such as Xilinx® Zynq®, Intel® SoC or Microchip SoC.
- On standalone FPGA boards, such as an Intel FPGA or a Xilinx FPGA board.
- On platforms that have a separate FPGA and processor, such as the Simulink Real-Time™ target machine with FPGA I/O boards.
If you are using an SoC platform or a platform that has a separate FPGA and processor, you can partition your design to generate hardware that targets the FPGA fabric and software that runs on the embedded processor of the target platform.
For more details on the workflow, see Targeting FPGA & SoC Hardware Overview. For more details on specific hardware platforms, see HDL Coder Supported Hardware.
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