How to Implement Configurable Sequence Reordering with N-Way Parallel Outputs Using HDL Coder?
3 vues (au cours des 30 derniers jours)
Afficher commentaires plus anciens
## Problem Description
Dear community members,
I am seeking guidance on implementing a configurable sequence reordering system with parallel outputs using HDL Coder. Here are the detailed requirements:
### Requirements
1. **Input Sequence**:
Continuous data stream:
$$ x_1, x_2, \dots, x_L, x_{L+1}, \dots, x_{NL} $$
2. **Output Structure**:
- **N parallel outputs** with **L+1 elements per output**.
- Adjacent outputs overlap by **1 element**:
- *Output 1*: $ \{x_1, x_2, \dots, x_L, x_{L+1}\} $
- *Output 2*: $ \{x_{L+1}, x_{L+2}, \dots, x_{2L}, x_{2L+1}\} $
- ...
- *Output N*: $ \{x_{(N-1)L+1}, \dots, x_{NL}\} $
3. **Configurable Parameters**:
- $ L $: Overlap interval (output length = $ L + 1 $).
- $ N $: Number of parallel output channels.
Thank you in advance for your expertise.
0 commentaires
Réponses (1)
Bharath Venkataraman
le 2 Juin 2025
Modifié(e) : Bharath Venkataraman
le 3 Juin 2025
The Tapped Delay block can give you the last L values (based on teh delay setting). You can add in additional logic to pick out the values at the times you need.
0 commentaires
Voir également
Catégories
En savoir plus sur FPGA, ASIC, and SoC Development dans Help Center et File Exchange
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!