Is it possible to achieve a 50% duty cycle while dividing a clock by a fractional number like 1.5?

I am modeling a frequency divider architecture in Simulink using a fractional division block with a DSM (Delta-Sigma Modulator). The division ratio I am testing is 1.5.

The issue I am facing is that the output clock does not have a 50% duty cycle. I understand that for odd or fractional division ratios, achieving a symmetric duty cycle is not straightforward, but I would like to know:

• Is it theoretically possible to achieve a clean 50% duty cycle for a fractional divider like ÷1.5?
• If yes, what is the recommended implementation method in Simulink or MATLAB? Should I toggle the output on half-period events, or is there another design approach?
• Any example models, block configurations, or references would be greatly appreciated.

Answer 1

[Walter Roberson]

You can only get 50% duty cycle if you divide the 1.5 by a further 4/3. That is, 3/2 * 4/3 == 2 and you need to end up with a divisor of 2 to get 50% duty cycle.

[Humayun]

So i cannot get my desired freq with 50% duty cycle, because if my desired frequency is (Fin/1.5) then it cannot be produced with 50% duty cycle?

[Walter Roberson]

With divisor of 1.5 you get 2/3 of the original frequency. That can only be converted to 50% duty cycle by dividing by a further 4/3.