makehdl('I​mageSharpe​ningHDLMod​el/Image Sharpening HDL System') fpga implementation problem

when i done with this, it generates hdl code but cntrl is single input by the frame to pixel block. where as image sharpenning HDL system generates extra inputs like ctrlIn_hStar, ctrlIn_vEnd, cntrln_valid ....so on. when this HDL coding block converts in to FIL block there actual interfacing problem comes in to the picture, how can i interface that extra inputs and extra output generated by the single cntrl from Frame to pixel and pixel to frame

Answer 1

[Tim McBrayer]

This is all part of the design process. Your model needs to read or drive these signals as appropriate.

The Vision HDL Toolbox featured examples, in the documentation, may provide you with some additional insight.

Answer 2

[Bharath Venkataraman]

You can feed in the single control bus into a Pixel Control Bus Selector block which will then send out 5 signals (hStart hEnd vStart vEnd valid). Alternatively, you can use the FIL Frame To Pixels blocks which does this for you and gives the output control signals.