Xilinx system generator Hardware co-simulation taking more time on FPGA

Hi there,

I have a Xilinx system generator design which takes around 4 mins to run on a host PC. But when i do hardware cosimulation on zed board it takes around 8-10 mins to run on hardware (ZED board). Can somebody tell me why this behavior?

Answer 1

[Marco]

Hello Sashi, probably in your simulation there is a bottleneck due to the fact the communication beetween the host and the Zed board is not ok. In particular, the co-simulation helps if you are offloading a significant portion of the computation. A good practice and a possible solution of problem: the host PC generates the input of the design only, instead you can move on the hardware the part of the design that required more computation.

BR Marco