Axi stream interface in Xilinx system generator
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Hello there, I am trying to implement the AXI stream interface to an image negative operation in system generator. I want to verify whether my design is correct to export as an IP, in terms of enabling the bus signals. (in simulation its working fine) thanks in advance.
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/160870/image.png)
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