Can I perform FPGA in the Loop with SysGen for DSP without HDL Coder and Verifier ?

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Yoni Levy
Yoni Levy le 9 Juin 2017
Commenté : Yoni Levy le 14 Juin 2017
Hi,
For my internship I have to implement FPGA in the Loop in Matlab. I have a licence for System Generator for DSP but it's not possible to have a license for HDL Coder or HDL Verifier. If I have already my VHDL code, it's possible to perform FIL with only SysGen for DSP ?
Thank you in advance

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Arnav Mendiratta
Arnav Mendiratta le 13 Juin 2017
No, You would need HDL Verifier for FIL Simulations. You can request a 1 month trial for free.

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