HDL workflow Advisor image

I will use the HDL workflow to do image processing on the FPGA.

How do I input the image will not be a bunch of interfaces?

My image is 2D, how does the test bench code describe it?

Answer 1

[Bharath Venkataraman]

This Vision HDL Toolbox page shows the capabilities provided for image processing on an FPGA. If you have the product, try doc visionhdl and look at the examples.

To target your design easily onto an FPGA, the Xilinx Zynq Support package will help.

[Eric Cigan]

Please note that starting with the 24a general release, the features of the Xilinx Zynq Support from Vision HDL Toolbox will be available thorugh Xilinx Zynq SoC Support from SoC Blockset.

Answer 2

[Eric Cigan]

Please note that starting with the 24a general release, the features of the Xilinx Zynq Support from Vision HDL Toolbox will be available thorugh Xilinx Zynq SoC Support from SoC Blockset.