Why can I not change the architecture of my subsystem to Black Box?

I am using R2018b. My end goal is to use FPGA in the Loop programming. I have verilog files that I want to include as a black box but I cannot change the architecture of my simulink subsystem to a blackbox.

Answer 1

[Raghav Singhal]

Please see this documentation page for details on generating a black box interface:

https://www.mathworks.com/help/hdlcoder/ug/black-box-implementation-for-subsystem-blocks.html

[dr446]

Thanks but I have already read it. For some reason, the subsystem is stuck at a module and cannot be changed to a black box.

Answer 2

[Antti Mattila]

I seem to have the same problem. The "BlackBox" architecture option is not available for a subsystem. (I'm using 2018b also).

For some subsystem/refrenced models it is. This seems arbitrary.

Answer 3

[Sina Aghli]

I'm having the same issue(R2019a), has this feature been deprecated?

[Sina Aghli]

I create a HDL/Subsystem and then rightckick then HDL Code -> HDL Block Properties ...

then in "HDL properties::Subsystem" window under Implementation->Architecture, the only available option is "Module" and there is no blackbox option