Generating HDL code error in the example "HDL Optimized QPSK Receiver with Captured Data"

I am doing the example for "HDL Optimized QPSK Receiver with Captured Data"(https://www.mathworks.com/help/comm/examples/hdl-optimized-qpsk-receiver-with-captured-data.html)

and got a below message.

1) Generating DUT using verilog was successful. (Default language was set to VDHL)

2) Generating Test bench was failed.

How can I fix it? Could you help me?

Answer 1

[Kiran Kintali]

This is a bug in HDL test bench generation. Please reach out to [e-mail] with reproduction steps.

[Kiran Kintali]

What version of MATLAB you are using when you encountered this error? Thanks.