Implementation Latency of Blackbox Subsystem when using oversampling

I have a Data Aquisition Module written in VHDL and inserted into Simulink via a DocBlock Blackbox Subsystem.(Matlab 2018a)

The blackbox outputs data at a low samplerate of 20kHz(And uses the FPGAs 50Mhz clock internally). It has a Latency of 750 clock cycles(50 Mhz clock) from aquisition trigger(which is supposed to be the 20kHz Clock Enable with Phase 0) to output. The data processing path afterwards runs at 20kHz with an oversampling factor of 2500.

My Problem: The Blackbox sample time in Simulink is configured at the low(20KHz) sample time. I want to process the data in the same 20 Khz period that it is aquired(but with a 750 cycle delay in oversampling cycles). But the Implementation Latency Parameter in HDLBlockProperties refers to the blocks sampling time(So 750 refers to 750x20kHz periods instead of 750x50Mhz periods).

Changing the Blackbox Sample Time to 50Mhz and using a Downsample(or Rate Transition) with a 750 cycle Sample Offset doesnt work either, because they both enforce maximum delay when used with the HDLCoder. (The Data is only available at the start of the next 20Khz cycle)

Is there a way to declare the Oversampling Pipeline depth of a Blackbox Implementation that I am missing? (So that the clock rate pipeline optimisations know about the 750 cycles for its pipeline budget)

The Picture shows the wanted behaviour.

Since I want to synchronize the data with other data aquired at the start of a 20KHz cycle, I can't move the aquisition point 750 cycles before the clock enable.

Thank you very much for your time.

[Dominique Görner]

As I understand it, the easiest way to allow this, is to allow disabling "enforce maximum delay" on downsample blocks. And then treating them as a block with the offset as an internal pipeline depth(indexed from the start of the slower rate), for use in Pipeline optimisation. This wouldn't allow Blackbox modules being used in the middle of a pipeline, but at least at the beginning, where external/blackbox IPs are more common.

The more ideal Solution would be to add a "Pipeline Latency" property to Blackbox subsystems, in order to include them anywhere in the chain. Or reference the Implementation Latency to the base(oversampling) clock.

This is of course just an outside view with now understanding of the inner workings and limitations of HDLCoder.

Answer 1

[Kiran Kintali]

Hi Dominque,

Is it possible to share a mockup model with the basic configuration of doc block based blackbox as you describe and corresponding upsample and downsample blocks?

This will help provide additional guidance based on the model sample time and oversampling requirements.

Thanks

[Dominique Görner]

I added a stripped down model of the fpga core.

The Top Model has Delay Balancing disabled.This way the Digital I/Os of the Current/Angle Sensors and the PWM dont get delayed. This is the solution I found to MATLAB Answers question.

The Blackbox in question is inside the "Pipelined Subsystem". It has no actual Latency, but should indicate the Latency of the ADC Conversion outside the "pipelined subsystem" through its settings. I know this is not a very pretty solution and would appreciate a solution that works without the dummy(also related to the other question).

(I added a commented version of the downsample on one of the current phases. It requires the sample time of the adc outputs to be set to 1/50000000.)

Thank you very much for your help!

[Dominique Görner]

So can i expect anything more here? This is sadly turning out to be a major bottleneck for my thesis.

Answer 2

[Kiran Kintali]

With HDLCoder we have done a very detailed Fied-Oriented Controller model on FPGA/SoC. See the attached document.

Happy to share more details and implementation models. Feel free to contact us [e-mail]

Thanks

Answer 3

[Kiran Kintali]

We are also able to generate code for the mockup model.