Complex to Magnitude-Angle HDL Optimized does not get converted to clock-rate

The "Complex to Magnitude-Angle HDL Optimized"-Block I use in order to calculate the atan2 of my alpha and beta components that come from my clarke-transfrom stays at the data-rate. All the other blocks get converted to the clock-rate in the generated-model as intendet by using the option "clock-rate pipelining".

I tried the oversampling factor and defining the sample-rate and data-rate through rate-transitions, either way the result stays identical.

Is there something I'm missing or do I have to force the block to its final sample-time?

[Kiran Kintali]

can you share a sample model with your clock rate pipelining requirements for additional guidance? Thanks

Answer 1

[Kiran Kintali]

The "Complex to Magnitude-Angle HDL Optimized" simulates latency in the original model and does not participate in clock rate pipelining where the latency is modeled at the data rate in the original model and hence currently does not participate in clock rate pipelining.

Please consider using CORDIC atan2 block in the Math library in the interim. We will be expanding on the capabilities of CMA block in the near future to support additional features.

[Manuel K]

Thanks for your quick answer.

This behavior is especially annoying because other blocks that implement there function using the CORDIC-algorithm (like sin, cos) have no latency and only show their real behavior in the generated model. The same applies for the "HDL Reciprocal"-Block, which uses the Newton-Raphson approximation.

Sadly the CORDIC atan2 block in the Math library does not support HDL code generation yet.

My solution now uses the genrated model with some modificatians (removed all the z^-1 blocks and used the "OutputPipeline" option instead).

I'm looking forward to future updates on these topics.

[Kiran Kintali]

May I know what release you are currently using?

I checked R2020b Pre-release; the following functions are indeed supported for HDL code generation.

Trigonometric Function block that has Function set to sin, cos, sincos, cos+jsin, or atan2 and Approximation method as CORDIC.

[Manuel K]

R2019a, but I will migrate to R2020b next week and test this.

This would be great!

[Manuel K]

[Kiran Kintali]

Thanks for pointing this out; atan2 CORDIC block is supported since 19b release. I have reported the discrepancy to the documentation team.

[Manuel K]

I'm now using the latest Simulink R2020a (Version 10.1).

Sadly using the Trigonometric Function Block set to atan2 and CORDIC does throw errors when running the Workflow Advisor. The Error: "Error Delay balancing unsuccessful because Delay introduced in feedback loop cannot be path balanced. Offending Block:controllerTB/control_system_mitreset/PLL/FlattenHierarchyon/Vektordreher-3/Trigonometric Function." is coming from an unrelated part of the system which will compile perfectly fine with the other solution ("Complex to Magnitude-Angle HDL Optimized").

The atan2-Block is not inside a feedback-loop, nethertheless I tried the tips mentioned in the documentation Trigonometric Function (Extended Capabilities - Restrictions), but this changed nothing.

When I open the generted model, the atan2-block did not get converted to the faster clock-rate and stayed at the original slower data-rate. But now it doesn't show the whole CORDIC-Algorithm anymore and just adds the delays like the sin/cos-blocks do.

I will try this with a minimalistic example again, but I don't think this will work.

Is there a working example anywhere?

Best Regards

Manuel

[Manuel K]

Also I can't seem to find a reference to this topic in the release notes from R2019x to R2020x.

[Kiran Kintali]

Attached is a basic CORDIC atan2 block in a feedback loop and with a specified oversampling factor that was able to generate code.

>> makehdl(gcb, 'OverSampling', 200)
### Generating HDL for 'cmagang_atan2_os_floop/cmag_atan2'.
### Using the config set for model cmagang_atan2_os_floop for HDL code generation parameters.
### Running HDL checks on the model 'cmagang_atan2_os_floop'.
### Begin compilation of the model 'cmagang_atan2_os_floop'...
### Applying HDL optimizations on the model 'cmagang_atan2_os_floop'...
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 0: 1 cycles.
### Begin model generation.
### Model generation complete.
### Begin VHDL Code Generation for 'cmagang_atan2_os_floop'.
### MESSAGE: The design requires 200 times faster clock with respect to the base rate = 1.
### Working on Trigonometric Function as hdl_prj\hdlsrc\cmagang_atan2_os_floop\Trigonometric_Function.vhd.
### Working on cmag_atan2_tc as hdl_prj\hdlsrc\cmagang_atan2_os_floop\cmag_atan2_tc.vhd.
### Working on cmagang_atan2_os_floop/cmag_atan2 as hdl_prj\hdlsrc\cmagang_atan2_os_floop\cmag_atan2.vhd.
### Code Generation for 'cmagang_atan2_os_floop' completed.
### Creating HDL Code Generation Check Report cmag_atan2_report.html
### HDL check for 'cmagang_atan2_os_floop' complete with 0 errors, 0 warnings, and 1 messages.
### HDL code generation complete.
>> 

[Manuel K]

Thanks for the example, but I'm unable to open it since I have only R2020a installed.

Apart from this, my scenario has no oversampling factor defined (1) because it is a multi-rate system whith parts already assigned to the clock-rate.

[Manuel K]

I managed to get my system working now.

The problem was that on of my custom library blocks was set to "atomic subsystem" and gets used multiple times inside my model and even once inside a feedback-loop. When I use the "Trigonometric Function"-block for the atan2-calculation instead of the "Complex to Magnitude-Angle HDL Optimized"-block, I had to disable the "Treat as atomic unit"-option for this block inside the feedback-loop.

The validation model and generated model work as intended now.

Finally I will test the generated code on my hardware